Add devicetree changes to enable MDSS display-subsystem,
display-controller(DPU), DisplayPort controller and eDP PHY for
Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 216 +++++++++++++++++++++++++++++++++-
1 file changed, 215 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 7ada029c32c1f2d0488a3fd1be603887c64bf4f9..93797696c72a2001dc0564454da281745f0a7433 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -4308,6 +4308,218 @@ camcc: clock-controller@ade0000 {
#power-domain-cells = <1>;
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,qcs8300-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ mdss_dp0_phy: phy@aec2a00 {
+ compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x0aec2a00 0x0 0x19c>,
+ <0x0 0x0aec2200 0x0 0xec>,
+ <0x0 0x0aec2600 0x0 0xec>,
+ <0x0 0x0aec2000 0x0 0x1c8>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,qcs8300-dp";
+
+ reg = <0x0 0x0af54000 0x0 0x200>,
+ <0x0 0x0af54200 0x0 0x200>,
+ <0x0 0x0af55000 0x0 0xc00>,
+ <0x0 0x0af56000 0x0 0x400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp0_phy 0>,
+ <&mdss_dp0_phy 1>,
+ <&mdss_dp0_phy 1>,
+ <&mdss_dp0_phy 1>;
+ phys = <&mdss_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sa8775p-dispcc0";
reg = <0x0 0x0af00000 0x0 0x20000>;
@@ -4315,7 +4527,9 @@ dispcc: clock-controller@af00000 {
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
- <0>, <0>, <0>, <0>,
+ <&mdss_dp0_phy 0>,
+ <&mdss_dp0_phy 1>,
+ <0>, <0>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
#clock-cells = <1>;
--
2.34.1On 7/30/25 11:49 AM, Yongxing Mou wrote: > Add devicetree changes to enable MDSS display-subsystem, > display-controller(DPU), DisplayPort controller and eDP PHY for > Qualcomm QCS8300 platform. > > Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> > --- [...] > + > + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; is this necessary? > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; interrupts-extended, file-wide Konrad
On 2025/7/30 18:25, Konrad Dybcio wrote: > On 7/30/25 11:49 AM, Yongxing Mou wrote: >> Add devicetree changes to enable MDSS display-subsystem, >> display-controller(DPU), DisplayPort controller and eDP PHY for >> Qualcomm QCS8300 platform. >> >> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >> --- > > [...] > >> + >> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; > > is this necessary? > Emm, i try to remove assigned-clocks and assigned-clock-rates here, device can still work.. here we just want to keep consistent with sa8775p. >> + >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0>; > > interrupts-extended, file-wide > > Konrad Sure. thanks~
On 8/4/25 6:39 AM, Yongxing Mou wrote: > > > On 2025/7/30 18:25, Konrad Dybcio wrote: >> On 7/30/25 11:49 AM, Yongxing Mou wrote: >>> Add devicetree changes to enable MDSS display-subsystem, >>> display-controller(DPU), DisplayPort controller and eDP PHY for >>> Qualcomm QCS8300 platform. >>> >>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >>> --- >> >> [...] >> >>> + >>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; >>> + assigned-clock-rates = <19200000>; >> >> is this necessary? >> > Emm, i try to remove assigned-clocks and assigned-clock-rates here, device can still work.. here we just want to keep consistent with sa8775p. Dmitry, do you remember whether this is some relic of the past that was required at one point? The driver lists 19.2 as the only possible frequency for the source of this branch Konrad
On Mon, Aug 04, 2025 at 02:34:56PM +0200, Konrad Dybcio wrote: > On 8/4/25 6:39 AM, Yongxing Mou wrote: > > > > > > On 2025/7/30 18:25, Konrad Dybcio wrote: > >> On 7/30/25 11:49 AM, Yongxing Mou wrote: > >>> Add devicetree changes to enable MDSS display-subsystem, > >>> display-controller(DPU), DisplayPort controller and eDP PHY for > >>> Qualcomm QCS8300 platform. > >>> > >>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> > >>> --- > >> > >> [...] > >> > >>> + > >>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; > >>> + assigned-clock-rates = <19200000>; > >> > >> is this necessary? > >> > > Emm, i try to remove assigned-clocks and assigned-clock-rates here, device can still work.. here we just want to keep consistent with sa8775p. > > Dmitry, do you remember whether this is some relic of the past that > was required at one point? I think it was necessary for old platforms (MSM8916, MSM8939, MSM8953, APQ8084, MSM8974, MSM8992/94, MSM8996, MSM8998, SDM630/660), which can source vsync_clk_src either from the XO or from the GPLL / MMPLL. > > The driver lists 19.2 as the only possible frequency for the source > of this branch -- With best wishes Dmitry
On 8/5/25 7:15 AM, Dmitry Baryshkov wrote: > On Mon, Aug 04, 2025 at 02:34:56PM +0200, Konrad Dybcio wrote: >> On 8/4/25 6:39 AM, Yongxing Mou wrote: >>> >>> >>> On 2025/7/30 18:25, Konrad Dybcio wrote: >>>> On 7/30/25 11:49 AM, Yongxing Mou wrote: >>>>> Add devicetree changes to enable MDSS display-subsystem, >>>>> display-controller(DPU), DisplayPort controller and eDP PHY for >>>>> Qualcomm QCS8300 platform. >>>>> >>>>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >>>>> --- >>>> >>>> [...] >>>> >>>>> + >>>>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; >>>>> + assigned-clock-rates = <19200000>; >>>> >>>> is this necessary? >>>> >>> Emm, i try to remove assigned-clocks and assigned-clock-rates here, device can still work.. here we just want to keep consistent with sa8775p. >> >> Dmitry, do you remember whether this is some relic of the past that >> was required at one point? > > I think it was necessary for old platforms (MSM8916, MSM8939, MSM8953, > APQ8084, MSM8974, MSM8992/94, MSM8996, MSM8998, SDM630/660), which can > source vsync_clk_src either from the XO or from the GPLL / MMPLL. The RCG has more than one input, but the Linux driver (checked about half of the ones you listed) only lists the XO-derived frequency so I'm not sure it was ever *really* an issue Konrad
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