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[PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU

Neil Armstrong posted 1 patch 2 months, 1 week ago 
arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
[PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Neil Armstrong 2 months, 1 week ago 
Update GPU node to include acd level values.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4127,72 +4127,84 @@ zap-shader {
 
 			/* Speedbin needs more work on A740+, keep only lower freqs */
 			gpu_opp_table: opp-table {
-				compatible = "operating-points-v2";
+				compatible = "operating-points-v2-adreno",
+					     "operating-points-v2";
 
 				opp-231000000 {
 					opp-hz = /bits/ 64 <231000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
 					opp-peak-kBps = <2136718>;
+					qcom,opp-acd-level = <0xc82f5ffd>;
 				};
 
 				opp-310000000 {
 					opp-hz = /bits/ 64 <310000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 					opp-peak-kBps = <2136718>;
+					qcom,opp-acd-level = <0xc82c5ffd>;
 				};
 
 				opp-366000000 {
 					opp-hz = /bits/ 64 <366000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
 					opp-peak-kBps = <6074218>;
+					qcom,opp-acd-level = <0xc02e5ffd>;
 				};
 
 				opp-422000000 {
 					opp-hz = /bits/ 64 <422000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 					opp-peak-kBps = <8171875>;
+					qcom,opp-acd-level = <0xc02d5ffd>;
 				};
 
 				opp-500000000 {
 					opp-hz = /bits/ 64 <500000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
 					opp-peak-kBps = <8171875>;
+					qcom,opp-acd-level = <0xc02a5ffd>;
 				};
 
 				opp-578000000 {
 					opp-hz = /bits/ 64 <578000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 					opp-peak-kBps = <8171875>;
+					qcom,opp-acd-level = <0x882c5ffd>;
 				};
 
 				opp-629000000 {
 					opp-hz = /bits/ 64 <629000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
 					opp-peak-kBps = <10687500>;
+					qcom,opp-acd-level = <0x882a5ffd>;
 				};
 
 				opp-680000000 {
 					opp-hz = /bits/ 64 <680000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 					opp-peak-kBps = <12449218>;
+					qcom,opp-acd-level = <0x882a5ffd>;
 				};
 
 				opp-720000000 {
 					opp-hz = /bits/ 64 <720000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 					opp-peak-kBps = <12449218>;
+					qcom,opp-acd-level = <0x882a5ffd>;
 				};
 
 				opp-770000000 {
 					opp-hz = /bits/ 64 <770000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 					opp-peak-kBps = <12449218>;
+					qcom,opp-acd-level = <0x882a5ffd>;
 				};
 
 				opp-834000000 {
 					opp-hz = /bits/ 64 <834000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 					opp-peak-kBps = <14398437>;
+					qcom,opp-acd-level = <0x882a5ffd>;
 				};
 			};
 		};

---
base-commit: 038d61fd642278bab63ee8ef722c50d10ab01e8f
change-id: 20250729-topic-sm8650-upstream-gpu-acd-level-1c430e7f158f

Best regards,
-- 
Neil Armstrong <neil.armstrong@linaro.org>
Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Bjorn Andersson 1 month, 3 weeks ago 
On Tue, 29 Jul 2025 16:40:53 +0200, Neil Armstrong wrote:
> Update GPU node to include acd level values.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sm8650: Add ACD levels for GPU
      commit: c2e07613b8d40f0ac60dd9b28c0dd15f9a298c11

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>
Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Akhil P Oommen 2 months, 1 week ago 
On 7/29/2025 8:10 PM, Neil Armstrong wrote:
> Update GPU node to include acd level values.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

-Akhil.

> ---
>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -4127,72 +4127,84 @@ zap-shader {
>  
>  			/* Speedbin needs more work on A740+, keep only lower freqs */
>  			gpu_opp_table: opp-table {
> -				compatible = "operating-points-v2";
> +				compatible = "operating-points-v2-adreno",
> +					     "operating-points-v2";
>  
>  				opp-231000000 {
>  					opp-hz = /bits/ 64 <231000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>  					opp-peak-kBps = <2136718>;
> +					qcom,opp-acd-level = <0xc82f5ffd>;
>  				};
>  
>  				opp-310000000 {
>  					opp-hz = /bits/ 64 <310000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>  					opp-peak-kBps = <2136718>;
> +					qcom,opp-acd-level = <0xc82c5ffd>;
>  				};
>  
>  				opp-366000000 {
>  					opp-hz = /bits/ 64 <366000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>  					opp-peak-kBps = <6074218>;
> +					qcom,opp-acd-level = <0xc02e5ffd>;
>  				};
>  
>  				opp-422000000 {
>  					opp-hz = /bits/ 64 <422000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>  					opp-peak-kBps = <8171875>;
> +					qcom,opp-acd-level = <0xc02d5ffd>;
>  				};
>  
>  				opp-500000000 {
>  					opp-hz = /bits/ 64 <500000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
>  					opp-peak-kBps = <8171875>;
> +					qcom,opp-acd-level = <0xc02a5ffd>;
>  				};
>  
>  				opp-578000000 {
>  					opp-hz = /bits/ 64 <578000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>  					opp-peak-kBps = <8171875>;
> +					qcom,opp-acd-level = <0x882c5ffd>;
>  				};
>  
>  				opp-629000000 {
>  					opp-hz = /bits/ 64 <629000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>  					opp-peak-kBps = <10687500>;
> +					qcom,opp-acd-level = <0x882a5ffd>;
>  				};
>  
>  				opp-680000000 {
>  					opp-hz = /bits/ 64 <680000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>  					opp-peak-kBps = <12449218>;
> +					qcom,opp-acd-level = <0x882a5ffd>;
>  				};
>  
>  				opp-720000000 {
>  					opp-hz = /bits/ 64 <720000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>  					opp-peak-kBps = <12449218>;
> +					qcom,opp-acd-level = <0x882a5ffd>;
>  				};
>  
>  				opp-770000000 {
>  					opp-hz = /bits/ 64 <770000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>  					opp-peak-kBps = <12449218>;
> +					qcom,opp-acd-level = <0x882a5ffd>;
>  				};
>  
>  				opp-834000000 {
>  					opp-hz = /bits/ 64 <834000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>  					opp-peak-kBps = <14398437>;
> +					qcom,opp-acd-level = <0x882a5ffd>;
>  				};
>  			};
>  		};
> 
> ---
> base-commit: 038d61fd642278bab63ee8ef722c50d10ab01e8f
> change-id: 20250729-topic-sm8650-upstream-gpu-acd-level-1c430e7f158f
> 
> Best regards,
Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Konrad Dybcio 2 months, 1 week ago 
On 7/29/25 4:40 PM, Neil Armstrong wrote:
> Update GPU node to include acd level values.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -4127,72 +4127,84 @@ zap-shader {
>  
>  			/* Speedbin needs more work on A740+, keep only lower freqs */
>  			gpu_opp_table: opp-table {
> -				compatible = "operating-points-v2";
> +				compatible = "operating-points-v2-adreno",
> +					     "operating-points-v2";
>  
>  				opp-231000000 {
>  					opp-hz = /bits/ 64 <231000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>  					opp-peak-kBps = <2136718>;
> +					qcom,opp-acd-level = <0xc82f5ffd>;
>  				};
>  
>  				opp-310000000 {
>  					opp-hz = /bits/ 64 <310000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>  					opp-peak-kBps = <2136718>;
> +					qcom,opp-acd-level = <0xc82c5ffd>;
>  				};

https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-devicetree/-/blob/gfx-devicetree-oss.lnx.1.0.r1-rel/gpu/pineapple-v2-gpu-pwrlevels.dtsi?ref_type=heads

doesn't set ACD for D1/D2

>  
>  				opp-366000000 {
>  					opp-hz = /bits/ 64 <366000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>  					opp-peak-kBps = <6074218>;
> +					qcom,opp-acd-level = <0xc02e5ffd>;

And other values differ too

What release did you grab these from?

Konrad
Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Neil Armstrong 2 months, 1 week ago 
On 30/07/2025 12:00, Konrad Dybcio wrote:
> On 7/29/25 4:40 PM, Neil Armstrong wrote:
>> Update GPU node to include acd level values.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
>>   1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -4127,72 +4127,84 @@ zap-shader {
>>   
>>   			/* Speedbin needs more work on A740+, keep only lower freqs */
>>   			gpu_opp_table: opp-table {
>> -				compatible = "operating-points-v2";
>> +				compatible = "operating-points-v2-adreno",
>> +					     "operating-points-v2";
>>   
>>   				opp-231000000 {
>>   					opp-hz = /bits/ 64 <231000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>>   					opp-peak-kBps = <2136718>;
>> +					qcom,opp-acd-level = <0xc82f5ffd>;
>>   				};
>>   
>>   				opp-310000000 {
>>   					opp-hz = /bits/ 64 <310000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>>   					opp-peak-kBps = <2136718>;
>> +					qcom,opp-acd-level = <0xc82c5ffd>;
>>   				};
> 
> https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-devicetree/-/blob/gfx-devicetree-oss.lnx.1.0.r1-rel/gpu/pineapple-v2-gpu-pwrlevels.dtsi?ref_type=heads
> 
> doesn't set ACD for D1/D2
> 
>>   
>>   				opp-366000000 {
>>   					opp-hz = /bits/ 64 <366000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>>   					opp-peak-kBps = <6074218>;
>> +					qcom,opp-acd-level = <0xc02e5ffd>;
> 
> And other values differ too
> 
> What release did you grab these from?

A much more recent non-public release with different gpu-pwrlevels for different SKU codes,
all sets ACDs for D1/D2, and the ACD values are:

#define ACD_LEVEL_TURBO_L1    0x882a5ffd
#define ACD_LEVEL_TURBO       0x882a5ffd
#define ACD_LEVEL_NOM_L1      0x882a5ffd
#define ACD_LEVEL_NOM         0x882a5ffd
#define ACD_LEVEL_SVS_L2      0x882a5ffd
#define ACD_LEVEL_SVS_L1      0x882a5ffd
#define ACD_LEVEL_SVS_L0      0x882a5ffd
#define ACD_LEVEL_SVS         0x882c5ffd
#define ACD_LEVEL_LOW_SVS_L1  0xc02a5ffd
#define ACD_LEVEL_LOW_SVS     0xc02d5ffd
#define ACD_LEVEL_LOW_SVS_D0  0xc02e5ffd
#define ACD_LEVEL_LOW_SVS_D1  0xc82c5ffd
#define ACD_LEVEL_LOW_SVS_D2  0xc82f5ffd

Neil

> 
> Konrad
Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU
Posted by Konrad Dybcio 2 months ago 
On 7/30/25 4:28 PM, Neil Armstrong wrote:
> On 30/07/2025 12:00, Konrad Dybcio wrote:
>> On 7/29/25 4:40 PM, Neil Armstrong wrote:
>>> Update GPU node to include acd level values.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
>>>   1 file changed, 13 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> @@ -4127,72 +4127,84 @@ zap-shader {
>>>                 /* Speedbin needs more work on A740+, keep only lower freqs */
>>>               gpu_opp_table: opp-table {
>>> -                compatible = "operating-points-v2";
>>> +                compatible = "operating-points-v2-adreno",
>>> +                         "operating-points-v2";
>>>                     opp-231000000 {
>>>                       opp-hz = /bits/ 64 <231000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>>>                       opp-peak-kBps = <2136718>;
>>> +                    qcom,opp-acd-level = <0xc82f5ffd>;
>>>                   };
>>>                     opp-310000000 {
>>>                       opp-hz = /bits/ 64 <310000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>>>                       opp-peak-kBps = <2136718>;
>>> +                    qcom,opp-acd-level = <0xc82c5ffd>;
>>>                   };
>>
>> https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-devicetree/-/blob/gfx-devicetree-oss.lnx.1.0.r1-rel/gpu/pineapple-v2-gpu-pwrlevels.dtsi?ref_type=heads
>>
>> doesn't set ACD for D1/D2
>>
>>>                     opp-366000000 {
>>>                       opp-hz = /bits/ 64 <366000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>>>                       opp-peak-kBps = <6074218>;
>>> +                    qcom,opp-acd-level = <0xc02e5ffd>;
>>
>> And other values differ too
>>
>> What release did you grab these from?
> 
> A much more recent non-public release with different gpu-pwrlevels for different SKU codes,
> all sets ACDs for D1/D2, and the ACD values are:
> 
> #define ACD_LEVEL_TURBO_L1    0x882a5ffd
> #define ACD_LEVEL_TURBO       0x882a5ffd
> #define ACD_LEVEL_NOM_L1      0x882a5ffd
> #define ACD_LEVEL_NOM         0x882a5ffd
> #define ACD_LEVEL_SVS_L2      0x882a5ffd
> #define ACD_LEVEL_SVS_L1      0x882a5ffd
> #define ACD_LEVEL_SVS_L0      0x882a5ffd
> #define ACD_LEVEL_SVS         0x882c5ffd
> #define ACD_LEVEL_LOW_SVS_L1  0xc02a5ffd
> #define ACD_LEVEL_LOW_SVS     0xc02d5ffd
> #define ACD_LEVEL_LOW_SVS_D0  0xc02e5ffd
> #define ACD_LEVEL_LOW_SVS_D1  0xc82c5ffd
> #define ACD_LEVEL_LOW_SVS_D2  0xc82f5ffd

I found sources confirming this, thanks

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

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