Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in the SpacemiT K1 SoC. The controller is based on the Synopsys
DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
DRD mode.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
---
.../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+ - Ze Huang <huang.ze@linux.dev>
+
+description: |
+ The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
+ for USB 3.0 and DRD for USB 2.0.
+
+ Key features:
+ - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+ - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+ - Internal DMA controller and flexible endpoint FIFO sizing
+
+ Communication Interface:
+ - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+ - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+properties:
+ compatible:
+ const: spacemit,k1-dwc3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: usbdrd30
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ items:
+ - description: phandle to USB2/HS PHY
+ - description: phandle to USB3/SS PHY
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ resets:
+ items:
+ - description: USB3.0 AHB reset
+ - description: USB3.0 VCC reset
+ - description: USB3.0 PHY reset
+ - description: PCIE0 global reset (for combo phy)
+
+ reset-names:
+ items:
+ - const: ahb
+ - const: vcc
+ - const: phy
+ - const: pcie0
+
+ reset-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 2
+ description: delay after reset sequence [us]
+
+ vbus-supply:
+ description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - phys
+ - phy-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0xc0a00000 0x10000>;
+ clocks = <&syscon_apmu 16>;
+ clock-names = "usbdrd30";
+ interrupts = <125>;
+ phys = <&usb2phy>, <&usb3phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ resets = <&syscon_apmu 8>,
+ <&syscon_apmu 9>,
+ <&syscon_apmu 10>,
+ <&syscon_apmu 26>;
+ reset-names = "ahb", "vcc", "phy", "pcie0";
+ reset-delay = <2>;
+ vbus-supply = <&usb3_vbus>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <1>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <2>;
+ vdd-supply = <&usb3_vhub>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 3 28 1>;
+ };
+ };
--
2.50.1On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in the SpacemiT K1 SoC. The controller is based on the Synopsys
> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> DRD mode.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Ze Huang <huang.ze@linux.dev>
> ---
Ze Huang:
I seen Krzysztof and Thinh Nguyen already acked this patches. Do you
wait for greg pick it up or need respin?
My one layerscape usb patch depend on this one!
Frank
> .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++
> 1 file changed, 124 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> @@ -0,0 +1,124 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
> +
> +maintainers:
> + - Ze Huang <huang.ze@linux.dev>
> +
> +description: |
> + The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
> + for USB 3.0 and DRD for USB 2.0.
> +
> + Key features:
> + - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
> + - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
> + - Internal DMA controller and flexible endpoint FIFO sizing
> +
> + Communication Interface:
> + - Use of PIPE3 (125MHz) interface for USB3.0 PHY
> + - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
> +
> +allOf:
> + - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> + compatible:
> + const: spacemit,k1-dwc3
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: usbdrd30
> +
> + interrupts:
> + maxItems: 1
> +
> + phys:
> + items:
> + - description: phandle to USB2/HS PHY
> + - description: phandle to USB3/SS PHY
> +
> + phy-names:
> + items:
> + - const: usb2-phy
> + - const: usb3-phy
> +
> + resets:
> + items:
> + - description: USB3.0 AHB reset
> + - description: USB3.0 VCC reset
> + - description: USB3.0 PHY reset
> + - description: PCIE0 global reset (for combo phy)
> +
> + reset-names:
> + items:
> + - const: ahb
> + - const: vcc
> + - const: phy
> + - const: pcie0
> +
> + reset-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 2
> + description: delay after reset sequence [us]
> +
> + vbus-supply:
> + description: A phandle to the regulator supplying the VBUS voltage.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - phys
> + - phy-names
> + - resets
> + - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + usb@c0a00000 {
> + compatible = "spacemit,k1-dwc3";
> + reg = <0xc0a00000 0x10000>;
> + clocks = <&syscon_apmu 16>;
> + clock-names = "usbdrd30";
> + interrupts = <125>;
> + phys = <&usb2phy>, <&usb3phy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + resets = <&syscon_apmu 8>,
> + <&syscon_apmu 9>,
> + <&syscon_apmu 10>,
> + <&syscon_apmu 26>;
> + reset-names = "ahb", "vcc", "phy", "pcie0";
> + reset-delay = <2>;
> + vbus-supply = <&usb3_vbus>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + hub_2_0: hub@1 {
> + compatible = "usb2109,2817";
> + reg = <1>;
> + vdd-supply = <&usb3_vhub>;
> + peer-hub = <&hub_3_0>;
> + reset-gpios = <&gpio 3 28 1>;
> + };
> +
> + hub_3_0: hub@2 {
> + compatible = "usb2109,817";
> + reg = <2>;
> + vdd-supply = <&usb3_vhub>;
> + peer-hub = <&hub_2_0>;
> + reset-gpios = <&gpio 3 28 1>;
> + };
> + };
>
> --
> 2.50.1
>
On Wed, Sep 10, 2025 at 06:18:39PM -0400, Frank Li wrote: > On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote: > > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded > > in the SpacemiT K1 SoC. The controller is based on the Synopsys > > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 > > DRD mode. > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Signed-off-by: Ze Huang <huang.ze@linux.dev> > > --- > > Ze Huang: > > I seen Krzysztof and Thinh Nguyen already acked this patches. Do you > wait for greg pick it up or need respin? > > My one layerscape usb patch depend on this one! > > Frank Hi Frank, I'll remove the PCIe reset in the update - since Alex's latest combo PHY work now manages this functionality. The patch is otherwise in good shape though. Look for the updated series from me before end of week. Best, Ze
On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote: > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded > in the SpacemiT K1 SoC. The controller is based on the Synopsys > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 > DRD mode. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Ze Huang <huang.ze@linux.dev> > --- > .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++ > 1 file changed, 124 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > @@ -0,0 +1,124 @@ ... > + resets: > + items: > + - description: USB3.0 AHB reset > + - description: USB3.0 VCC reset > + - description: USB3.0 PHY reset > + - description: PCIE0 global reset (for combo phy) Why should the USB driver takes care of the PCIe stuff? This sounds strange to me. > + reset-names: > + items: > + - const: ahb > + - const: vcc > + - const: phy > + - const: pcie0 Best regards, Yao Zi
On Tue, Jul 29, 2025 at 01:41:01AM +0000, Yao Zi wrote: > On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote: > > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded > > in the SpacemiT K1 SoC. The controller is based on the Synopsys > > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 > > DRD mode. > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Signed-off-by: Ze Huang <huang.ze@linux.dev> > > --- > > .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++ > > 1 file changed, 124 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > > @@ -0,0 +1,124 @@ > > ... > > > + resets: > > + items: > > + - description: USB3.0 AHB reset > > + - description: USB3.0 VCC reset > > + - description: USB3.0 PHY reset > > + - description: PCIE0 global reset (for combo phy) > > Why should the USB driver takes care of the PCIe stuff? This sounds > strange to me. > On K1, PHY depends on the clocks and resets it shares with the controller, and the controller driver is guarantees that any needed clocks are enabled, and any resets that affect the PHY are de-asserted before using the PHY. RESET_PCIE0_GLOBAL reset is necessary during, and only, the calibration stage of combo phy. To simplify both the driver architecture and the device tree files, RESET_PCIE0_GLOBAL (and some other clk/reset) are now managed by the relevant controller driver (either USB3 or PCIe0) instead of PHY driver. Only one of USB3.0 SuperSpeed and PCIe-0 will be activated in a boot. PCIe-0 will not be affected when it's working. Hi Alex, please correct me if anything wrong > > + reset-names: > > + items: > > + - const: ahb > > + - const: vcc > > + - const: phy > > + - const: pcie0 > > Best regards, > Yao Zi > > >
On Tue, Jul 29, 2025 at 01:58:12PM +0800, Ze Huang wrote: > On Tue, Jul 29, 2025 at 01:41:01AM +0000, Yao Zi wrote: > > On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote: > > > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded > > > in the SpacemiT K1 SoC. The controller is based on the Synopsys > > > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 > > > DRD mode. > > > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > Signed-off-by: Ze Huang <huang.ze@linux.dev> > > > --- > > > .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++ > > > 1 file changed, 124 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > > > new file mode 100644 > > > index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml > > > @@ -0,0 +1,124 @@ > > > > ... > > > > > + resets: > > > + items: > > > + - description: USB3.0 AHB reset > > > + - description: USB3.0 VCC reset > > > + - description: USB3.0 PHY reset > > > + - description: PCIE0 global reset (for combo phy) > > > > Why should the USB driver takes care of the PCIe stuff? This sounds > > strange to me. > > > > On K1, PHY depends on the clocks and resets it shares with the controller, > and the controller driver is guarantees that any needed clocks are enabled, > and any resets that affect the PHY are de-asserted before using the PHY. So does the "PCIe0 global reset" make effects to both USB3 and PCIe **controllers**? If not, this is something wrong in the devicetree side. > RESET_PCIE0_GLOBAL reset is necessary during, and only, the calibration stage > of combo phy. If it's only used by PHY, why couldn't it be a property of the PHY? Sorry, but I still cannot get the point. Regards, Yao Zi > To simplify both the driver architecture and the device tree files, > RESET_PCIE0_GLOBAL (and some other clk/reset) are now managed by the > relevant controller driver (either USB3 or PCIe0) instead of PHY driver. > > Only one of USB3.0 SuperSpeed and PCIe-0 will be activated in a boot. > PCIe-0 will not be affected when it's working.
On 29/07/2025 07:58, Ze Huang wrote: > On Tue, Jul 29, 2025 at 01:41:01AM +0000, Yao Zi wrote: >> On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote: >>> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded >>> in the SpacemiT K1 SoC. The controller is based on the Synopsys >>> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 >>> DRD mode. >>> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> Signed-off-by: Ze Huang <huang.ze@linux.dev> >>> --- >>> .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++ >>> 1 file changed, 124 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml >>> new file mode 100644 >>> index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml >>> @@ -0,0 +1,124 @@ >> >> ... >> >>> + resets: >>> + items: >>> + - description: USB3.0 AHB reset >>> + - description: USB3.0 VCC reset >>> + - description: USB3.0 PHY reset >>> + - description: PCIE0 global reset (for combo phy) >> >> Why should the USB driver takes care of the PCIe stuff? This sounds >> strange to me. >> > > On K1, PHY depends on the clocks and resets it shares with the controller, > and the controller driver is guarantees that any needed clocks are enabled, > and any resets that affect the PHY are de-asserted before using the PHY. > > RESET_PCIE0_GLOBAL reset is necessary during, and only, the calibration stage > of combo phy. But this is not PCI! Why would you call it "I need to reset PCI" while you describe the USB device? Best regards, Krzysztof
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