On Mon, Jul 28, 2025 at 05:29:43PM +0200, Clément Le Goffic wrote:
> DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC.
> It allows to monitor DDR events that come from the DDR Controller
> such as read or write events.
>
> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
> ---
> .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 94 ++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml
> new file mode 100644
> index 000000000000..1d97861e3d44
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> + - Clément Le Goffic <legoffic.clement@gmail.com>
> +
> +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM)
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: st,stm32mp131-ddr-pmu
> + - items:
> + - enum:
> + - st,stm32mp151-ddr-pmu
> + - const: st,stm32mp131-ddr-pmu
> + - items:
> + - const: st,stm32mp251-ddr-pmu
This and the 1st entry can be a single enum.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + access-controllers:
> + minItems: 1
> + maxItems: 2
> +
> + memory-channel:
> + description:
> + The memory channel this DDRPERFM is attached to.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: st,stm32mp131-ddr-pmu
> + then:
> + required:
> + - clocks
> + - resets
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: st,stm32mp251-ddr-pmu
> + then:
> + required:
> + - access-controllers
> + - memory-channel
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/stm32mp1-clks.h>
> + #include <dt-bindings/reset/stm32mp1-resets.h>
> +
> + perf@5a007000 {
> + compatible = "st,stm32mp151-ddr-pmu", "st,stm32mp131-ddr-pmu";
> + reg = <0x5a007000 0x400>;
> + clocks = <&rcc DDRPERFM>;
> + resets = <&rcc DDRPERFM_R>;
> + };
> +
> + - |
> + ddr_channel: sdram-channel-0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "jedec,ddr4-channel";
> + io-width = <16>;
> + };
> +
> + perf@48041000 {
> + compatible = "st,stm32mp251-ddr-pmu";
> + reg = <0x48041000 0x400>;
> + access-controllers = <&rcc 104>;
> + memory-channel = <&ddr_channel>;
> + };
>
> --
> 2.43.0
>