CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
Add support for the APSS PLL, RCG and clock enable for ipq5424.
The PLL, RCG register space are clubbed. Hence adding new APSS driver
for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
modeled as ICC clock. The L3 pll needs to be scaled along with the CPU.
v2: https://lore.kernel.org/linux-arm-msm/20250723110815.2865403-1-quic_varada@quicinc.com/
v1: https://lore.kernel.org/linux-arm-msm/20250127093128.2611247-1-quic_srichara@quicinc.com/
Md Sadre Alam (1):
cpufreq: qcom-nvmem: Enable cpufreq for ipq5424
Sricharan Ramabadhran (3):
dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock
controller
clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller
arm64: dts: qcom: ipq5424: Enable cpufreq
.../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 ++++
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 61 ++++
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq5424.c | 260 ++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +
include/dt-bindings/clock/qcom,apss-ipq.h | 6 +
.../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
9 files changed, 405 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
create mode 100644 drivers/clk/qcom/apss-ipq5424.c
--
2.34.1