MediaTek devicetree/bindings warnings sanitization

[PATCH 19/38] arm64: dts: mediatek: mt6795: Add mediatek,infracfg to iommu node

Posted by AngeloGioacchino Del Regno 1 month, 2 weeks ago

The "M4U" IOMMU requires a handle to the infracfg to switch to
the 4gb/pae addressing mode: add it.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index e5e269a660b1..38f65aad2802 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -427,6 +427,7 @@ iommu: iommu@10205000 {
 			clocks = <&infracfg CLK_INFRA_M4U>;
 			clock-names = "bclk";
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
+			mediatek,infracfg = <&infracfg>;
 			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
 			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
 			#iommu-cells = <1>;
-- 
2.50.1

Re: [PATCH 19/38] arm64: dts: mediatek: mt6795: Add mediatek,infracfg to iommu node

Posted by Fei Shao 1 month, 1 week ago

On Thu, Jul 24, 2025 at 5:49 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> The "M4U" IOMMU requires a handle to the infracfg to switch to
> the 4gb/pae addressing mode: add it.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Fei Shao <fshao@chromium.org>

> ---
>  arch/arm64/boot/dts/mediatek/mt6795.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> index e5e269a660b1..38f65aad2802 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> @@ -427,6 +427,7 @@ iommu: iommu@10205000 {
>                         clocks = <&infracfg CLK_INFRA_M4U>;
>                         clock-names = "bclk";
>                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
> +                       mediatek,infracfg = <&infracfg>;
>                         mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
>                         power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
>                         #iommu-cells = <1>;
> --
> 2.50.1
>
>