From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.
Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add #interconnect-cells to help enable L3 pll as ICC clock
Add master/slave ids
---
.../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 +++++++++++++++++++
include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
.../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
3 files changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
new file mode 100644
index 000000000000..abb9eb78d271
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APSS IPQ5424 Clock Controller
+
+maintainers:
+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+ - Md Sadre Alam <quic_mdalam@quicinc.com>
+
+description: |
+ The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
+ The RCG and PLL have a separate register space from the GCC.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5424-apss-clk
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference to the XO clock.
+ - description: Reference to the GPLL0 clock.
+
+ clock-names:
+ items:
+ - const: xo
+ - const: gpll0
+
+ '#clock-cells':
+ const: 1
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#interconnect-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+
+ apss_clk: apss-clock@fa80000 {
+ compatible = "qcom,ipq5424-apss-clk";
+ reg = <0x0fa80000 0x20000>;
+ clocks = <&xo_board>, <&gcc GPLL0>;
+ clock-names = "xo", "gpll0";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
index 77b6e05492e2..0bb41e5efdef 100644
--- a/include/dt-bindings/clock/qcom,apss-ipq.h
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -8,5 +8,11 @@
#define APCS_ALIAS0_CLK_SRC 0
#define APCS_ALIAS0_CORE_CLK 1
+#define APSS_PLL_EARLY 2
+#define APSS_SILVER_CLK_SRC 3
+#define APSS_SILVER_CORE_CLK 4
+#define L3_PLL 5
+#define L3_CLK_SRC 6
+#define L3_CORE_CLK 7
#endif
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index a770356112ee..afd7e0683a24 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -21,4 +21,7 @@
#define MASTER_CNOC_USB 16
#define SLAVE_CNOC_USB 17
+#define MASTER_CPU 0
+#define SLAVE_L3 1
+
#endif /* INTERCONNECT_QCOM_IPQ5424_H */
--
2.34.1On Wed, Jul 23, 2025 at 04:38:12PM +0530, Varadarajan Narayanan wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>
> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> The RCG and PLL have a separate register space from the GCC.
> Also the L3 cache has a separate pll and needs to be scaled along
> with the CPU.
>
> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> [ Added interconnect related changes ]
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v2: Add #interconnect-cells to help enable L3 pll as ICC clock
> Add master/slave ids
and v1 was where? I cannot find it in the inbox, no lore links.
> ---
> .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 +++++++++++++++++++
> include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
> .../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
> 3 files changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> new file mode 100644
> index 000000000000..abb9eb78d271
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm APSS IPQ5424 Clock Controller
> +
> +maintainers:
> + - Sricharan Ramabadhran <quic_srichara@quicinc.com>
> + - Md Sadre Alam <quic_mdalam@quicinc.com>
Are you sure? Why they do not send their code then? Usually sending
other poeple's code means they do not care or moved on or changed jobs.
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> + The RCG and PLL have a separate register space from the GCC.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq5424-apss-clk
Missing blank line
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Reference to the XO clock.
> + - description: Reference to the GPLL0 clock.
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: gpll0
You do not name the inputs according how provider calls them. You name
them based on the INPUT. pll? source? bus?
> +
> + '#clock-cells':
> + const: 1
> +
> + '#interconnect-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#interconnect-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> +
> + apss_clk: apss-clock@fa80000 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Best regards,
Krzysztof
On Thu, Jul 24, 2025 at 10:14:01AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Jul 23, 2025 at 04:38:12PM +0530, Varadarajan Narayanan wrote:
> > From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >
> > The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> > The RCG and PLL have a separate register space from the GCC.
> > Also the L3 cache has a separate pll and needs to be scaled along
> > with the CPU.
> >
> > Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> > [ Added interconnect related changes ]
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > v2: Add #interconnect-cells to help enable L3 pll as ICC clock
> > Add master/slave ids
>
> and v1 was where? I cannot find it in the inbox, no lore links.
v1 - https://lore.kernel.org/linux-arm-msm/20250127093128.2611247-1-quic_srichara@quicinc.com/
Will add this while posting the next version.
> > ---
> > .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 61 +++++++++++++++++++
> > include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
> > .../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
> > 3 files changed, 70 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> > new file mode 100644
> > index 000000000000..abb9eb78d271
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm APSS IPQ5424 Clock Controller
> > +
> > +maintainers:
> > + - Sricharan Ramabadhran <quic_srichara@quicinc.com>
> > + - Md Sadre Alam <quic_mdalam@quicinc.com>
>
> Are you sure? Why they do not send their code then? Usually sending
> other poeple's code means they do not care or moved on or changed jobs.
They changed projects. Shall I append myself to the above list
or replace them with myself.
> > +
> > +description: |
>
> Do not need '|' unless you need to preserve formatting.
ok.
> > + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> > + The RCG and PLL have a separate register space from the GCC.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,ipq5424-apss-clk
>
> Missing blank line
ok.
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Reference to the XO clock.
> > + - description: Reference to the GPLL0 clock.
> > +
> > + clock-names:
> > + items:
> > + - const: xo
> > + - const: gpll0
>
> You do not name the inputs according how provider calls them. You name
> them based on the INPUT. pll? source? bus?
Will check and update.
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > + '#interconnect-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > + - '#interconnect-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> > +
> > + apss_clk: apss-clock@fa80000 {
>
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Thanks for the feedback. Will post a new version addressing these.
-Varada
© 2016 - 2026 Red Hat, Inc.