If the DMA_BUS_MODE_SFT_RESET bit is 1 before software reset,
there is no need to do anything for this abnormal case, just
return -EINVAL immediately in loongson_dwmac_fix_reset().

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index e1591e6217d4..6d10077666c7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -513,6 +513,9 @@ static int loongson_dwmac_fix_reset(void *priv, void __iomem *ioaddr)
 {
 	u32 value = readl(ioaddr + DMA_BUS_MODE);
 
+	if (value & DMA_BUS_MODE_SFT_RESET)
+		return -EINVAL;
+
 	value |= DMA_BUS_MODE_SFT_RESET;
 	writel(value, ioaddr + DMA_BUS_MODE);
 
-- 
2.42.0

On Tue, 22 Jul 2025 14:27:15 +0800
Tiezhu Yang <yangtiezhu@loongson.cn> wrote:

> If the DMA_BUS_MODE_SFT_RESET bit is 1 before software reset,
> there is no need to do anything for this abnormal case, just
> return -EINVAL immediately in loongson_dwmac_fix_reset().
> 
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>

Do you know when that could ever happen ? I'm asking because this logic
for the DMA reset is duplicated in several places in this driver, maybe
this could be useful for other users as well. I'm guessing this is to
avoid waiting for the timeout when the DMA reset fails, but that is
usually when there's a missing clock somewhere (such as the RGMII clock
from the PHY), in which case I don't think the RST bit will be set.

Maxime

On 2025/7/22 下午8:48, Maxime Chevallier wrote:
> On Tue, 22 Jul 2025 14:27:15 +0800
> Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
> 
>> If the DMA_BUS_MODE_SFT_RESET bit is 1 before software reset,
>> there is no need to do anything for this abnormal case, just
>> return -EINVAL immediately in loongson_dwmac_fix_reset().
>>
>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> 
> Do you know when that could ever happen ? I'm asking because this logic
> for the DMA reset is duplicated in several places in this driver, maybe
> this could be useful for other users as well. I'm guessing this is to
> avoid waiting for the timeout when the DMA reset fails, but that is
> usually when there's a missing clock somewhere (such as the RGMII clock
> from the PHY), in which case I don't think the RST bit will be set.

To be honest, I am not quite sure the root cause but this actually
happened on the test environment, I guess there is a missing clock.

You are right, the initial aim of this patch is to return early for
this case to avoid waiting for the timeout when the DMA reset fails.

Thanks,
Tiezhu

On 2025/7/22 下午9:10, Tiezhu Yang wrote:
> On 2025/7/22 下午8:48, Maxime Chevallier wrote:
>> On Tue, 22 Jul 2025 14:27:15 +0800
>> Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>>
>>> If the DMA_BUS_MODE_SFT_RESET bit is 1 before software reset,
>>> there is no need to do anything for this abnormal case, just
>>> return -EINVAL immediately in loongson_dwmac_fix_reset().
>>>
>>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
>>
>> Do you know when that could ever happen ? I'm asking because this logic
>> for the DMA reset is duplicated in several places in this driver, maybe
>> this could be useful for other users as well. I'm guessing this is to
>> avoid waiting for the timeout when the DMA reset fails, but that is
>> usually when there's a missing clock somewhere (such as the RGMII clock
>> from the PHY), in which case I don't think the RST bit will be set.
> 
> To be honest, I am not quite sure the root cause but this actually
> happened on the test environment, I guess there is a missing clock.
> 
> You are right, the initial aim of this patch is to return early for
> this case to avoid waiting for the timeout when the DMA reset fails.

With the help of hardware engineer to analysis the ‌device‌ of mainboard,
the root cause is that the MAC controller does not connect to any PHY
interface, there is a missing clock, so the DMA reset fails.

I will send v2 later to update the commit message if it makes sense.

Thanks,
Tiezhu