This patch series improves RISC-V kernel compatibility and robustness by
refining how the SATP mode is determined during early boot. Some RISC-V
implementations, such as the Anlogic DR1V90 FPSoC with a UX900 RISC-V
core designed by Nuclei, which I am currently attempting to run the
mainline kernel on [1], may hang when attempting to write an unsupported
SATP mode.

To address this, the patch determines the SATP mode limit by taking the
minimum of the value specified by the kernel command line option
("noXlvl", e.g., "no4lvl" or "no5lvl") and the "mmu-type" property in
the device tree for the first enabled CPU. If only one is specified,
that value will be used as the limit.

- If the resulting SATP mode limit is sv48 or higher, the kernel will
  probe SATP modes from this limit down to lower modes until a supported
  mode is found.
- If the limit is sv39, the kernel will directly use sv39 without
  probing lower modes.

Link: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech [1]
---
Junhui Liu (2):
      riscv: mm: Return intended SATP mode for noXlvl options
      riscv: mm: Use mmu-type from FDT to limit SATP mode

 arch/riscv/kernel/pi/cmdline_early.c |  4 ++--
 arch/riscv/kernel/pi/fdt_early.c     | 40 ++++++++++++++++++++++++++++++++++++
 arch/riscv/kernel/pi/pi.h            |  1 +
 arch/riscv/mm/init.c                 | 11 +++++++---
 4 files changed, 51 insertions(+), 5 deletions(-)
---
base-commit: 89be9a83ccf1f88522317ce02f854f30d6115c41
change-id: 20250713-satp-from-fdt-c22c245c27e9

Best regards,
-- 
Junhui Liu <junhui.liu@pigmoral.tech>