[v1] riscv: Add initial support for Anlogic DR1V90

[PATCH RFC 06/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart

Posted by Junhui Liu 2 months, 2 weeks ago

The Anlogic DR1V90 SoC integrates a UART controller compatible with
snps,dw-apb-uart, operating at a 50 MHz clock.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 8f1b7f704c5bc7cb9552b7d4825d96199cbc6c4f..ed00eefe17aa11200e0a10637d4cc10b68948699 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -51,6 +51,7 @@ properties:
           - const: renesas,rzn1-uart
       - items:
           - enum:
+              - anlogic,dr1v90-uart
               - brcm,bcm11351-dw-apb-uart
               - brcm,bcm21664-dw-apb-uart
               - rockchip,px30-uart

-- 
2.50.1

Re: [PATCH RFC 06/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart

Posted by Rob Herring (Arm) 2 months, 1 week ago

On Mon, 21 Jul 2025 23:46:12 +0800, Junhui Liu wrote:
> The Anlogic DR1V90 SoC integrates a UART controller compatible with
> snps,dw-apb-uart, operating at a 50 MHz clock.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>