Add the IFPC restore register list and enable IFPC support on Adreno
X1-85 gpu.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
3 files changed, 78 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
+/* Applicable for X185, A750 */
+static const u32 a750_ifpc_reglist_regs[] = {
+ REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
+ REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
+ REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
+ REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
+ REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
+ REG_A6XX_TPL1_NC_MODE_CNTL,
+ REG_A6XX_SP_NC_MODE_CNTL,
+ REG_A6XX_CP_DBG_ECO_CNTL,
+ REG_A6XX_CP_PROTECT_CNTL,
+ REG_A6XX_CP_PROTECT(0),
+ REG_A6XX_CP_PROTECT(1),
+ REG_A6XX_CP_PROTECT(2),
+ REG_A6XX_CP_PROTECT(3),
+ REG_A6XX_CP_PROTECT(4),
+ REG_A6XX_CP_PROTECT(5),
+ REG_A6XX_CP_PROTECT(6),
+ REG_A6XX_CP_PROTECT(7),
+ REG_A6XX_CP_PROTECT(8),
+ REG_A6XX_CP_PROTECT(9),
+ REG_A6XX_CP_PROTECT(10),
+ REG_A6XX_CP_PROTECT(11),
+ REG_A6XX_CP_PROTECT(12),
+ REG_A6XX_CP_PROTECT(13),
+ REG_A6XX_CP_PROTECT(14),
+ REG_A6XX_CP_PROTECT(15),
+ REG_A6XX_CP_PROTECT(16),
+ REG_A6XX_CP_PROTECT(17),
+ REG_A6XX_CP_PROTECT(18),
+ REG_A6XX_CP_PROTECT(19),
+ REG_A6XX_CP_PROTECT(20),
+ REG_A6XX_CP_PROTECT(21),
+ REG_A6XX_CP_PROTECT(22),
+ REG_A6XX_CP_PROTECT(23),
+ REG_A6XX_CP_PROTECT(24),
+ REG_A6XX_CP_PROTECT(25),
+ REG_A6XX_CP_PROTECT(26),
+ REG_A6XX_CP_PROTECT(27),
+ REG_A6XX_CP_PROTECT(28),
+ REG_A6XX_CP_PROTECT(29),
+ REG_A6XX_CP_PROTECT(30),
+ REG_A6XX_CP_PROTECT(31),
+ REG_A6XX_CP_PROTECT(32),
+ REG_A6XX_CP_PROTECT(33),
+ REG_A6XX_CP_PROTECT(34),
+ REG_A6XX_CP_PROTECT(35),
+ REG_A6XX_CP_PROTECT(36),
+ REG_A6XX_CP_PROTECT(37),
+ REG_A6XX_CP_PROTECT(38),
+ REG_A6XX_CP_PROTECT(39),
+ REG_A6XX_CP_PROTECT(40),
+ REG_A6XX_CP_PROTECT(41),
+ REG_A6XX_CP_PROTECT(42),
+ REG_A6XX_CP_PROTECT(43),
+ REG_A6XX_CP_PROTECT(44),
+ REG_A6XX_CP_PROTECT(45),
+ REG_A6XX_CP_PROTECT(46),
+ REG_A6XX_CP_PROTECT(47),
+};
+
+DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
+
static const struct adreno_info a7xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1432,12 +1495,13 @@ static const struct adreno_info a7xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV |
- ADRENO_QUIRK_PREEMPTION,
+ ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC,
.init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
+ .ifpc_reglist = &a750_ifpc_reglist,
.gmu_chipid = 0x7050001,
.gmu_cgc_mode = 0x00020202,
},
@@ -1459,6 +1523,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
+ .ifpc_reglist = &a750_ifpc_reglist,
.gmu_chipid = 0x7090100,
.gmu_cgc_mode = 0x00020202,
.bcms = (const struct a6xx_bcm[]) {
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 54decb9908fe526ac7f150465034b03ba688aa6d..bc9463840c02c3c3ee3ae0431eff147ae97edc88 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -809,11 +809,10 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
u32 *dest = (u32 *)&lock->regs[0];
int i;
- reglist = adreno_gpu->info->a6xx->pwrup_reglist;
-
lock->gpu_req = lock->cpu_req = lock->turn = 0;
- lock->ifpc_list_len = 0;
- lock->preemption_list_len = reglist->count;
+
+ reglist = adreno_gpu->info->a6xx->ifpc_reglist;
+ lock->ifpc_list_len = reglist->count;
/*
* For each entry in each of the lists, write the offset and the current
@@ -824,6 +823,14 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
*dest++ = gpu_read(gpu, reglist->regs[i]);
}
+ reglist = adreno_gpu->info->a6xx->pwrup_reglist;
+ lock->preemption_list_len = reglist->count;
+
+ for (i = 0; i < reglist->count; i++) {
+ *dest++ = reglist->regs[i];
+ *dest++ = gpu_read(gpu, reglist->regs[i]);
+ }
+
/*
* The overall register list is composed of
* 1. Static IFPC-only registers
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index bd1194bd15bf013489140c5f9f6b9f8582532a13..ed98dd1bd887bd160f73f320366a7b8b2c9f874e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -41,6 +41,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
const struct adreno_reglist_list *pwrup_reglist;
+ const struct adreno_reglist_list *ifpc_reglist;
u32 gmu_chipid;
u32 gmu_cgc_mode;
u32 prim_fifo_threshold;
--
2.50.1On 20/07/2025 14:16, Akhil P Oommen wrote:
> Add the IFPC restore register list and enable IFPC support on Adreno
> X1-85 gpu.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> 3 files changed, 78 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>
<snip>
> +
> static const struct adreno_info a7xx_gpus[] = {
> {
> .chip_ids = ADRENO_CHIP_IDS(0x07000200),
> @@ -1432,12 +1495,13 @@ static const struct adreno_info a7xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> ADRENO_QUIRK_HAS_HW_APRIV |
> - ADRENO_QUIRK_PREEMPTION,
> + ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC,
> .init = a6xx_gpu_init,
> .a6xx = &(const struct a6xx_info) {
> .hwcg = a740_hwcg,
> .protect = &a730_protect,
> .pwrup_reglist = &a7xx_pwrup_reglist,
> + .ifpc_reglist = &a750_ifpc_reglist,
> .gmu_chipid = 0x7050001,
> .gmu_cgc_mode = 0x00020202,
> },
> @@ -1459,6 +1523,7 @@ static const struct adreno_info a7xx_gpus[] = {
> .a6xx = &(const struct a6xx_info) {
> .protect = &a730_protect,
> .pwrup_reglist = &a7xx_pwrup_reglist,
> + .ifpc_reglist = &a750_ifpc_reglist,
So far it's stable on a750 so I think can safely add ADRENO_QUIRK_IFPC here aswell.
Neil
<snip>
On 7/29/2025 7:36 PM, neil.armstrong@linaro.org wrote:
> On 20/07/2025 14:16, Akhil P Oommen wrote:
>> Add the IFPC restore register list and enable IFPC support on Adreno
>> X1-85 gpu.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 +++++++++++++++++++++
>> +++++++++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> 3 files changed, 78 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/
>> drm/msm/adreno/a6xx_catalog.c
>> index
>> 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[]
>> = {
>>
>
> <snip>
>
>> +
>> static const struct adreno_info a7xx_gpus[] = {
>> {
>> .chip_ids = ADRENO_CHIP_IDS(0x07000200),
>> @@ -1432,12 +1495,13 @@ static const struct adreno_info a7xx_gpus[] = {
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + ADRENO_QUIRK_PREEMPTION | ADRENO_QUIRK_IFPC,
>> .init = a6xx_gpu_init,
>> .a6xx = &(const struct a6xx_info) {
>> .hwcg = a740_hwcg,
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> + .ifpc_reglist = &a750_ifpc_reglist,
>> .gmu_chipid = 0x7050001,
>> .gmu_cgc_mode = 0x00020202,
>> },
>> @@ -1459,6 +1523,7 @@ static const struct adreno_info a7xx_gpus[] = {
>> .a6xx = &(const struct a6xx_info) {
>> .protect = &a730_protect,
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> + .ifpc_reglist = &a750_ifpc_reglist,
>
> So far it's stable on a750 so I think can safely add ADRENO_QUIRK_IFPC
> here aswell.
Thanks for testing. I will enable it for a750 in the next revision.
-Akhil
>
> Neil
>
> <snip>
>
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Add the IFPC restore register list and enable IFPC support on Adreno
> X1-85 gpu.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> 3 files changed, 78 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>
> DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
>
> +/* Applicable for X185, A750 */
> +static const u32 a750_ifpc_reglist_regs[] = {
> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
> + REG_A6XX_TPL1_NC_MODE_CNTL,
> + REG_A6XX_SP_NC_MODE_CNTL,
> + REG_A6XX_CP_DBG_ECO_CNTL,
> + REG_A6XX_CP_PROTECT_CNTL,
> + REG_A6XX_CP_PROTECT(0),
> + REG_A6XX_CP_PROTECT(1),
Is it fair to assume that we'd like to saverestore all CP_PROT
registers on all SKUs, always? We can save some space in .rodata
this way..
Konrad
On 7/22/2025 8:25 PM, Konrad Dybcio wrote:
> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>> Add the IFPC restore register list and enable IFPC support on Adreno
>> X1-85 gpu.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> 3 files changed, 78 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>>
>> DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
>>
>> +/* Applicable for X185, A750 */
>> +static const u32 a750_ifpc_reglist_regs[] = {
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
>> + REG_A6XX_TPL1_NC_MODE_CNTL,
>> + REG_A6XX_SP_NC_MODE_CNTL,
>> + REG_A6XX_CP_DBG_ECO_CNTL,
>> + REG_A6XX_CP_PROTECT_CNTL,
>> + REG_A6XX_CP_PROTECT(0),
>> + REG_A6XX_CP_PROTECT(1),
>
> Is it fair to assume that we'd like to saverestore all CP_PROT
> registers on all SKUs, always? We can save some space in .rodata
> this way..
Yeah. Makes sense, but lets do that when we duplicate it in future.
-Akhil
>
> Konrad
On Sun, Jul 20, 2025 at 05:46:17PM +0530, Akhil P Oommen wrote: > Add the IFPC restore register list and enable IFPC support on Adreno > X1-85 gpu. Nit: GPU I can't stop but notice that KGSL enables IFPC for a bigger set of SKUs, starting from a630v2 and a615. Is there a plan to get IFPC supported on those platforms? > > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++-- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > 3 files changed, 78 insertions(+), 5 deletions(-) > -- With best wishes Dmitry
On 7/22/2025 7:25 PM, Dmitry Baryshkov wrote: > On Sun, Jul 20, 2025 at 05:46:17PM +0530, Akhil P Oommen wrote: >> Add the IFPC restore register list and enable IFPC support on Adreno >> X1-85 gpu. > > Nit: GPU > > I can't stop but notice that KGSL enables IFPC for a bigger set of > SKUs, starting from a630v2 and a615. Is there a plan to get IFPC > supported on those platforms? Sorry, no access to those hardwares. But I can certainly help if someone wants to do that. :) -Akhil. > >> >> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++-- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >> 3 files changed, 78 insertions(+), 5 deletions(-) >> >
On 7/22/25 11:37 PM, Akhil P Oommen wrote: > On 7/22/2025 7:25 PM, Dmitry Baryshkov wrote: >> On Sun, Jul 20, 2025 at 05:46:17PM +0530, Akhil P Oommen wrote: >>> Add the IFPC restore register list and enable IFPC support on Adreno >>> X1-85 gpu. >> >> Nit: GPU >> >> I can't stop but notice that KGSL enables IFPC for a bigger set of >> SKUs, starting from a630v2 and a615. Is there a plan to get IFPC >> supported on those platforms? > > Sorry, no access to those hardwares. But I can certainly help if someone > wants to do that. :) Let's get the groundwork merged first ;) Nowadays you can reasonably assume we have access to at least one board, no matter which SoC Konrad
On 7/23/2025 4:03 PM, Konrad Dybcio wrote: > On 7/22/25 11:37 PM, Akhil P Oommen wrote: >> On 7/22/2025 7:25 PM, Dmitry Baryshkov wrote: >>> On Sun, Jul 20, 2025 at 05:46:17PM +0530, Akhil P Oommen wrote: >>>> Add the IFPC restore register list and enable IFPC support on Adreno >>>> X1-85 gpu. >>> >>> Nit: GPU >>> >>> I can't stop but notice that KGSL enables IFPC for a bigger set of >>> SKUs, starting from a630v2 and a615. Is there a plan to get IFPC >>> supported on those platforms? >> >> Sorry, no access to those hardwares. But I can certainly help if someone >> wants to do that. :) > > Let's get the groundwork merged first ;) > > Nowadays you can reasonably assume we have access to at least one board, > no matter which SoC We just need to add a proper ifpc restore register list for most chipsets. But the legacy gmu firmware (a630 derivatives) might have some quirks. -Akhil. > > Konrad
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