From: Li Liu <quic_lliu6@quicinc.com>
Add display MDSS and DSI configuration for QCS615 platform.
QCS615 has a DP port, and DP support will be added in a later patch.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 181 ++++++++++++++++++++++++++++++++++-
1 file changed, 180 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 142338069a74cc6c263e17d84efa22ccd0c26813..24299430b195026e896c365d80a0036713f00d35 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -3372,12 +3373,190 @@ camcc: clock-controller@ad00000 {
#power-domain-cells = <1>;
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,sm6150-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm6150-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-25600000 {
+ opp-hz = /bits/ 64 <25600000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x0ae94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm6150-dsi-phy-14nm";
+ reg = <0x0 0x0ae94400 0x0 0x100>,
+ <0x0 0x0ae94500 0x0 0x300>,
+ <0x0 0x0ae94800 0x0 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <0>,
+ <0>,
+ <0>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1On 18/07/2025 14:56, Fange Zhang wrote: > From: Li Liu <quic_lliu6@quicinc.com> > > Add display MDSS and DSI configuration for QCS615 platform. > QCS615 has a DP port, and DP support will be added in a later patch. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Li Liu <quic_lliu6@quicinc.com> > Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 181 ++++++++++++++++++++++++++++++++++- > 1 file changed, 180 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 142338069a74cc6c263e17d84efa22ccd0c26813..24299430b195026e896c365d80a0036713f00d35 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -10,6 +10,7 @@ > #include <dt-bindings/clock/qcom,qcs615-videocc.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/gpio/gpio.h> Don't add completely redundant/unused headers. Drop Best regards, Krzysztof
On 7/29/2025 8:36 PM, Krzysztof Kozlowski wrote: > On 18/07/2025 14:56, Fange Zhang wrote: >> From: Li Liu <quic_lliu6@quicinc.com> >> >> Add display MDSS and DSI configuration for QCS615 platform. >> QCS615 has a DP port, and DP support will be added in a later patch. >> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Signed-off-by: Li Liu <quic_lliu6@quicinc.com> >> Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 181 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 180 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 142338069a74cc6c263e17d84efa22ccd0c26813..24299430b195026e896c365d80a0036713f00d35 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -10,6 +10,7 @@ >> #include <dt-bindings/clock/qcom,qcs615-videocc.h> >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/dma/qcom-gpi.h> >> +#include <dt-bindings/gpio/gpio.h> > > Don't add completely redundant/unused headers. > > Drop Got it, will remove it in next patch> > > Best regards, > Krzysztof
On 7/18/25 2:56 PM, Fange Zhang wrote:
> From: Li Liu <quic_lliu6@quicinc.com>
>
> Add display MDSS and DSI configuration for QCS615 platform.
> QCS615 has a DP port, and DP support will be added in a later patch.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
> Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
> ---
[...]
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm6150-dpu";
> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
> + <0x0 0x0aeb0000 0x0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "bus", "core", "vsync";
1 per line please, everywhere> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
Is this necessary?
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_CX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
interrupts-extended
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
Please keep a \n between properties and subnodes
> + dpu_intf0_out: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&mdss_dsi0_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-19200000 {
> + opp-hz = /bits/ 64 <19200000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-25600000 {
> + opp-hz = /bits/ 64 <25600000>;
> + required-opps = <&rpmhpd_opp_svs>;
This and the above frequency are missing one zero (i.e. you
have a 10x underclock)
[...]
> + mdss_dsi0_phy: phy@ae94400 {
> + compatible = "qcom,sm6150-dsi-phy-14nm";
> + reg = <0x0 0x0ae94400 0x0 0x100>,
> + <0x0 0x0ae94500 0x0 0x300>,
> + <0x0 0x0ae94800 0x0 0x188>;
sz = 0x124
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> + };
> +
> dispcc: clock-controller@af00000 {
> compatible = "qcom,qcs615-dispcc";
> reg = <0 0x0af00000 0 0x20000>;
>
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
> + <&mdss_dsi0_phy 0>,
> + <&mdss_dsi0_phy 1>,
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
Konrad
On 7/29/2025 7:17 PM, Konrad Dybcio wrote:
> On 7/18/25 2:56 PM, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add display MDSS and DSI configuration for QCS615 platform.
>> QCS615 has a DP port, and DP support will be added in a later patch.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
>> ---
>
> [...]
>
>> +
>> + mdss_mdp: display-controller@ae01000 {
>> + compatible = "qcom,sm6150-dpu";
>> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
>> + <0x0 0x0aeb0000 0x0 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface", "bus", "core", "vsync";
>
> 1 per line please, everywhere> +
Got it will fix it in next patch>> + assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>
> Is this necessary?
test pass without this, so will remove them in next patch>
>> +
>> + operating-points-v2 = <&mdp_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>
> interrupts-extended
Got it, will change it as below in next patch
interrupts-extended = <&mdss 0>;>
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>
> Please keep a \n between properties and subnodes
will fix it in next patch>
>> + dpu_intf0_out: endpoint {
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> + };
>> +
>> + mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-19200000 {
>> + opp-hz = /bits/ 64 <19200000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-25600000 {
>> + opp-hz = /bits/ 64 <25600000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>
> This and the above frequency are missing one zero (i.e. you
> have a 10x underclock)
Got it, will fix it in next patch>
> [...]
>
>> + mdss_dsi0_phy: phy@ae94400 {
>> + compatible = "qcom,sm6150-dsi-phy-14nm";
>> + reg = <0x0 0x0ae94400 0x0 0x100>,
>> + <0x0 0x0ae94500 0x0 0x300>,
>> + <0x0 0x0ae94800 0x0 0x188>;
>
> sz = 0x124
Got it, will change 0x188 to 0x124 in next patch>
>> + reg-names = "dsi_phy",
>> + "dsi_phy_lane",
>> + "dsi_pll";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface", "ref";
>> +
>> + status = "disabled";
>> + };
>> + };
>> +
>> dispcc: clock-controller@af00000 {
>> compatible = "qcom,qcs615-dispcc";
>> reg = <0 0x0af00000 0 0x20000>;
>>
>> clocks = <&rpmhcc RPMH_CXO_CLK>,
>> - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
>> + <&mdss_dsi0_phy 0>,
>> + <&mdss_dsi0_phy 1>,
>
> #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>Got it, will add the h file and change as below in next patch
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,>
> Konrad
On 8/5/25 2:24 PM, Fange Zhang wrote:
>
>
> On 7/29/2025 7:17 PM, Konrad Dybcio wrote:
>> On 7/18/25 2:56 PM, Fange Zhang wrote:
>>> From: Li Liu <quic_lliu6@quicinc.com>
>>>
>>> Add display MDSS and DSI configuration for QCS615 platform.
>>> QCS615 has a DP port, and DP support will be added in a later patch.
>>>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>> Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +
>>> + mdss_mdp: display-controller@ae01000 {
>>> + compatible = "qcom,sm6150-dpu";
>>> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
>>> + <0x0 0x0aeb0000 0x0 0x2008>;
>>> + reg-names = "mdp", "vbif";
>>> +
>>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>>> + clock-names = "iface", "bus", "core", "vsync";
>>
>> 1 per line please, everywhere> +
> Got it will fix it in next patch>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>>> + assigned-clock-rates = <19200000>;
>>
>> Is this necessary?
> test pass without this, so will remove them in next patch>
You need to leave a \n before you start typing your reply, otherwise
the email text gets messed up (like above)
Konrad
On 8/5/2025 8:26 PM, Konrad Dybcio wrote:
> On 8/5/25 2:24 PM, Fange Zhang wrote:
>>
>>
>> On 7/29/2025 7:17 PM, Konrad Dybcio wrote:
>>> On 7/18/25 2:56 PM, Fange Zhang wrote:
>>>> From: Li Liu <quic_lliu6@quicinc.com>
>>>>
>>>> Add display MDSS and DSI configuration for QCS615 platform.
>>>> QCS615 has a DP port, and DP support will be added in a later patch.
>>>>
>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>>>> Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
>>>> ---
>>>
>>> [...]
>>>
>>>> +
>>>> + mdss_mdp: display-controller@ae01000 {
>>>> + compatible = "qcom,sm6150-dpu";
>>>> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
>>>> + <0x0 0x0aeb0000 0x0 0x2008>;
>>>> + reg-names = "mdp", "vbif";
>>>> +
>>>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>>>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>>>> + clock-names = "iface", "bus", "core", "vsync";
>>>
>>> 1 per line please, everywhere> +
>> Got it will fix it in next patch>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>>>> + assigned-clock-rates = <19200000>;
>>>
>>> Is this necessary?
>> test pass without this, so will remove them in next patch>
>
> You need to leave a \n before you start typing your reply, otherwise
> the email text gets messed up (like above)
Got it, sorry for the mess>
> Konrad
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