PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
enumerates new link capabilities and status added for Gen 6 devices. One
of the link details enumerated in that register block is the "Segment
Captured" status in the Device Status 3 register. That status is
relevant for enabling IDE (Integrity & Data Encryption) whereby
Selective IDE streams can be limited to a given Requester ID range
within a given segment.
If a device has captured its Segment value then it knows that PCIe Flit
Mode is enabled via all links in the path that a configuration write
traversed. IDE establishment requires that "Segment Base" in
IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be
programmed if the RID association mechanism is in effect.
When / if IDE + Flit Mode capable devices arrive, the PCI core needs to
setup the segment base when using the RID association facility, but no
known deployments today depend on this.
Cc: Lukas Wunner <lukas@wunner.de>
Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Samuel Ortiz <sameo@rivosinc.com>
Cc: Alexey Kardashevskiy <aik@amd.com>
Cc: Xu Yilun <yilun.xu@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/pci/probe.c | 12 ++++++++++++
include/linux/pci.h | 1 +
include/uapi/linux/pci_regs.h | 7 +++++++
3 files changed, 20 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e19e7a926423..9ed25035a06d 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2271,6 +2271,17 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
return 0;
}
+static void pci_dev3_init(struct pci_dev *pdev)
+{
+ u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3);
+ u32 val = 0;
+
+ if (!cap)
+ return;
+ pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val);
+ pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT);
+}
+
/**
* pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
* @dev: PCI device to query
@@ -2625,6 +2636,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
pci_doe_init(dev); /* Data Object Exchange */
pci_tph_init(dev); /* TLP Processing Hints */
pci_rebar_init(dev); /* Resizable BAR */
+ pci_dev3_init(dev); /* Device 3 capabilities */
pci_ide_init(dev); /* Link Integrity and Data Encryption */
pcie_report_downtraining(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 0e5703fad0f6..a7353df51fea 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -444,6 +444,7 @@ struct pci_dev {
unsigned int pasid_enabled:1; /* Process Address Space ID */
unsigned int pri_enabled:1; /* Page Request Interface */
unsigned int tph_enabled:1; /* TLP Processing Hints */
+ unsigned int fm_enabled:1; /* Flit Mode (segment captured) */
unsigned int is_managed:1; /* Managed via devres */
unsigned int is_msi_managed:1; /* MSI release via devres installed */
unsigned int needs_freset:1; /* Requires fundamental reset */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 1b991a88c19c..2d49a4786a9f 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -751,6 +751,7 @@
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
+#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */
#define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */
#define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT
@@ -1227,6 +1228,12 @@
/* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE
+/* Device 3 Extended Capability */
+#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */
+#define PCI_DEV3_CTL 0x8 /* Device 3 Control Register */
+#define PCI_DEV3_STA 0xc /* Device 3 Status Register */
+#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */
+
/* Compute Express Link (CXL r3.1, sec 8.1.5) */
#define PCI_DVSEC_CXL_PORT 3
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
--
2.50.1
On Thu, Jul 17, 2025 at 11:33:54AM -0700, Dan Williams wrote:
> PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
> enumerates new link capabilities and status added for Gen 6 devices. One
> of the link details enumerated in that register block is the "Segment
> Captured" status in the Device Status 3 register. That status is
> relevant for enabling IDE (Integrity & Data Encryption) whereby
> Selective IDE streams can be limited to a given Requester ID range
> within a given segment.
>
> If a device has captured its Segment value then it knows that PCIe Flit
> Mode is enabled via all links in the path that a configuration write
> traversed. IDE establishment requires that "Segment Base" in
> IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be
> programmed if the RID association mechanism is in effect.
>
> When / if IDE + Flit Mode capable devices arrive, the PCI core needs to
> setup the segment base when using the RID association facility, but no
> known deployments today depend on this.
>
> Cc: Lukas Wunner <lukas@wunner.de>
> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Samuel Ortiz <sameo@rivosinc.com>
> Cc: Alexey Kardashevskiy <aik@amd.com>
> Cc: Xu Yilun <yilun.xu@linux.intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/probe.c | 12 ++++++++++++
> include/linux/pci.h | 1 +
> include/uapi/linux/pci_regs.h | 7 +++++++
> 3 files changed, 20 insertions(+)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index e19e7a926423..9ed25035a06d 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2271,6 +2271,17 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
> return 0;
> }
>
> +static void pci_dev3_init(struct pci_dev *pdev)
> +{
> + u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3);
> + u32 val = 0;
> +
> + if (!cap)
> + return;
> + pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val);
> + pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT);
> +}
> +
> /**
> * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
> * @dev: PCI device to query
> @@ -2625,6 +2636,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
> pci_doe_init(dev); /* Data Object Exchange */
> pci_tph_init(dev); /* TLP Processing Hints */
> pci_rebar_init(dev); /* Resizable BAR */
> + pci_dev3_init(dev); /* Device 3 capabilities */
> pci_ide_init(dev); /* Link Integrity and Data Encryption */
>
> pcie_report_downtraining(dev);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0e5703fad0f6..a7353df51fea 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -444,6 +444,7 @@ struct pci_dev {
> unsigned int pasid_enabled:1; /* Process Address Space ID */
> unsigned int pri_enabled:1; /* Page Request Interface */
> unsigned int tph_enabled:1; /* TLP Processing Hints */
> + unsigned int fm_enabled:1; /* Flit Mode (segment captured) */
> unsigned int is_managed:1; /* Managed via devres */
> unsigned int is_msi_managed:1; /* MSI release via devres installed */
> unsigned int needs_freset:1; /* Requires fundamental reset */
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 1b991a88c19c..2d49a4786a9f 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -751,6 +751,7 @@
> #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
> #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
> #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
> +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */
> #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */
> #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */
> #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT
> @@ -1227,6 +1228,12 @@
> /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */
> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE
>
> +/* Device 3 Extended Capability */
> +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */
> +#define PCI_DEV3_CTL 0x8 /* Device 3 Control Register */
> +#define PCI_DEV3_STA 0xc /* Device 3 Status Register */
> +#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */
> +
> /* Compute Express Link (CXL r3.1, sec 8.1.5) */
> #define PCI_DVSEC_CXL_PORT 3
> #define PCI_DVSEC_CXL_PORT_CTL 0x0c
> --
> 2.50.1
>
On Thu, Jul 17, 2025 at 11:33:54AM -0700, Dan Williams wrote:
> PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
> enumerates new link capabilities and status added for Gen 6 devices. One
s/ added for Gen 6 devices//
I know the "Gen 6 device" terminology is pervasive, but the spec
suggests avoiding it because it's so ambiguous.
> of the link details enumerated in that register block is the "Segment
> Captured" status in the Device Status 3 register. That status is
> relevant for enabling IDE (Integrity & Data Encryption) whereby
> Selective IDE streams can be limited to a given Requester ID range
> within a given segment.
>
> If a device has captured its Segment value then it knows that PCIe Flit
> Mode is enabled via all links in the path that a configuration write
> traversed. IDE establishment requires that "Segment Base" in
> IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be
> programmed if the RID association mechanism is in effect.
>
> When / if IDE + Flit Mode capable devices arrive, the PCI core needs to
> setup the segment base when using the RID association facility, but no
> known deployments today depend on this.
So far this mentions a lot of facts, but only the subject hints at
what it does. I guess it just captures the Flit Mode status, inferred
by Segment Captured?
I'm OK with basically just saying *that*, and moving some of the
implications to places where we depend on them.
> Cc: Lukas Wunner <lukas@wunner.de>
> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Samuel Ortiz <sameo@rivosinc.com>
> Cc: Alexey Kardashevskiy <aik@amd.com>
> Cc: Xu Yilun <yilun.xu@linux.intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/pci/probe.c | 12 ++++++++++++
> include/linux/pci.h | 1 +
> include/uapi/linux/pci_regs.h | 7 +++++++
> 3 files changed, 20 insertions(+)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index e19e7a926423..9ed25035a06d 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2271,6 +2271,17 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
> return 0;
> }
>
> +static void pci_dev3_init(struct pci_dev *pdev)
> +{
> + u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3);
> + u32 val = 0;
> +
> + if (!cap)
> + return;
> + pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val);
> + pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT);
> +}
> +
> /**
> * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
> * @dev: PCI device to query
> @@ -2625,6 +2636,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
> pci_doe_init(dev); /* Data Object Exchange */
> pci_tph_init(dev); /* TLP Processing Hints */
> pci_rebar_init(dev); /* Resizable BAR */
> + pci_dev3_init(dev); /* Device 3 capabilities */
> pci_ide_init(dev); /* Link Integrity and Data Encryption */
>
> pcie_report_downtraining(dev);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0e5703fad0f6..a7353df51fea 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -444,6 +444,7 @@ struct pci_dev {
> unsigned int pasid_enabled:1; /* Process Address Space ID */
> unsigned int pri_enabled:1; /* Page Request Interface */
> unsigned int tph_enabled:1; /* TLP Processing Hints */
> + unsigned int fm_enabled:1; /* Flit Mode (segment captured) */
> unsigned int is_managed:1; /* Managed via devres */
> unsigned int is_msi_managed:1; /* MSI release via devres installed */
> unsigned int needs_freset:1; /* Requires fundamental reset */
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 1b991a88c19c..2d49a4786a9f 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -751,6 +751,7 @@
> #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
> #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
> #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
> +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */
> #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */
> #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */
> #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT
> @@ -1227,6 +1228,12 @@
> /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */
> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE
>
> +/* Device 3 Extended Capability */
> +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */
> +#define PCI_DEV3_CTL 0x8 /* Device 3 Control Register */
> +#define PCI_DEV3_STA 0xc /* Device 3 Status Register */
> +#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */
> +
> /* Compute Express Link (CXL r3.1, sec 8.1.5) */
> #define PCI_DVSEC_CXL_PORT 3
> #define PCI_DVSEC_CXL_PORT_CTL 0x0c
> --
> 2.50.1
>
Bjorn Helgaas wrote: > On Thu, Jul 17, 2025 at 11:33:54AM -0700, Dan Williams wrote: > > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure, > > enumerates new link capabilities and status added for Gen 6 devices. One > > s/ added for Gen 6 devices// > > I know the "Gen 6 device" terminology is pervasive, but the spec > suggests avoiding it because it's so ambiguous. Ok. > > > of the link details enumerated in that register block is the "Segment > > Captured" status in the Device Status 3 register. That status is > > relevant for enabling IDE (Integrity & Data Encryption) whereby > > Selective IDE streams can be limited to a given Requester ID range > > within a given segment. > > > > If a device has captured its Segment value then it knows that PCIe Flit > > Mode is enabled via all links in the path that a configuration write > > traversed. IDE establishment requires that "Segment Base" in > > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be > > programmed if the RID association mechanism is in effect. > > > > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to > > setup the segment base when using the RID association facility, but no > > known deployments today depend on this. > > So far this mentions a lot of facts, but only the subject hints at > what it does. I guess it just captures the Flit Mode status, inferred > by Segment Captured? > > I'm OK with basically just saying *that*, and moving some of the > implications to places where we depend on them. Agree, too wordy. Trimmed to: PCIe r7.0 Section 7.7.9 Device 3 Extended Capability Structure, defines the canonical location for determining the Flit Mode of a device. This status is a dependency for PCIe IDE enabling. Add a new fm_enabled flag to 'struct pci_dev'.
On Thu, 17 Jul 2025 11:33:54 -0700 Dan Williams <dan.j.williams@intel.com> wrote: > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure, > enumerates new link capabilities and status added for Gen 6 devices. One > of the link details enumerated in that register block is the "Segment > Captured" status in the Device Status 3 register. That status is > relevant for enabling IDE (Integrity & Data Encryption) whereby > Selective IDE streams can be limited to a given Requester ID range > within a given segment. > > If a device has captured its Segment value then it knows that PCIe Flit > Mode is enabled via all links in the path that a configuration write > traversed. IDE establishment requires that "Segment Base" in > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be > programmed if the RID association mechanism is in effect. > > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to > setup the segment base when using the RID association facility, but no > known deployments today depend on this. > > Cc: Lukas Wunner <lukas@wunner.de> > Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > Cc: Bjorn Helgaas <bhelgaas@google.com> > Cc: Samuel Ortiz <sameo@rivosinc.com> > Cc: Alexey Kardashevskiy <aik@amd.com> > Cc: Xu Yilun <yilun.xu@linux.intel.com> > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 1b991a88c19c..2d49a4786a9f 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -751,6 +751,7 @@ > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ > #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ > #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > @@ -1227,6 +1228,12 @@ > /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE > > +/* Device 3 Extended Capability */ > +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */ Similar to earlier cases I'd make these 0x04 etc just to copy local style + match spec. > +#define PCI_DEV3_CTL 0x8 /* Device 3 Control Register */ > +#define PCI_DEV3_STA 0xc /* Device 3 Status Register */ > +#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */ > + > /* Compute Express Link (CXL r3.1, sec 8.1.5) */ > #define PCI_DVSEC_CXL_PORT 3 > #define PCI_DVSEC_CXL_PORT_CTL 0x0c
Jonathan Cameron wrote: [..] > > index 1b991a88c19c..2d49a4786a9f 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -751,6 +751,7 @@ > > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > > +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ > > #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ > > #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > > @@ -1227,6 +1228,12 @@ > > /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ > > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE > > > > +/* Device 3 Extended Capability */ > > +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */ > > Similar to earlier cases I'd make these 0x04 etc just to copy local style + match spec. Done.
Jonathan Cameron wrote: > On Thu, 17 Jul 2025 11:33:54 -0700 > Dan Williams <dan.j.williams@intel.com> wrote: > > > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure, > > enumerates new link capabilities and status added for Gen 6 devices. One > > of the link details enumerated in that register block is the "Segment > > Captured" status in the Device Status 3 register. That status is > > relevant for enabling IDE (Integrity & Data Encryption) whereby > > Selective IDE streams can be limited to a given Requester ID range > > within a given segment. > > > > If a device has captured its Segment value then it knows that PCIe Flit > > Mode is enabled via all links in the path that a configuration write > > traversed. IDE establishment requires that "Segment Base" in > > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be > > programmed if the RID association mechanism is in effect. > > > > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to > > setup the segment base when using the RID association facility, but no > > known deployments today depend on this. > > > > Cc: Lukas Wunner <lukas@wunner.de> > > Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > > Cc: Bjorn Helgaas <bhelgaas@google.com> > > Cc: Samuel Ortiz <sameo@rivosinc.com> > > Cc: Alexey Kardashevskiy <aik@amd.com> > > Cc: Xu Yilun <yilun.xu@linux.intel.com> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index 1b991a88c19c..2d49a4786a9f 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -751,6 +751,7 @@ > > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > > +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ > > #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ > > #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > > @@ -1227,6 +1228,12 @@ > > /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ > > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE > > > > +/* Device 3 Extended Capability */ > > +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */ > > Similar to earlier cases I'd make these 0x04 etc just to copy local style + match spec. Done.
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