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[PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Tomer Maimon posted 2 patches 2 months, 3 weeks ago
There is a newer version of this series
[PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes
Posted by Tomer Maimon 2 months, 3 weeks ago 
Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by
adding device nodes for Ethernet controllers, MMC controller, SPI
controllers, USB device controllers, random number generator, ADC,
PWM-FAN controller, I2C controllers, and PECI interface.
Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and
aliases for device access.
This patch enhances functionality for NPCM845-EVB platform.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
 1 file changed, 445 insertions(+)

diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
index 2638ee1c3846..46d5bd1c2129 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -10,6 +10,42 @@ / {
 
 	aliases {
 		serial0 = &serial0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		ethernet3 = &gmac3;
+		mdio-gpio0 = &mdio0;
+		mdio-gpio1 = &mdio1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
+		fiu3 = &fiu1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		i2c16 = &i2c16;
+		i2c17 = &i2c17;
+		i2c18 = &i2c18;
+		i2c19 = &i2c19;
+		i2c20 = &i2c20;
+		i2c21 = &i2c21;
+		i2c22 = &i2c22;
+		i2c23 = &i2c23;
+		i2c24 = &i2c24;
+		i2c25 = &i2c25;
+		i2c26 = &i2c26;
 	};
 
 	chosen {
@@ -25,12 +61,421 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;
+		};
+	};
+
+	mdio0: mdio@0 {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+			<&gpio1 26 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+		};
+	};
+
+	mdio1: mdio@1 {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
+			<&gpio2 28 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy1: ethernet-phy@1 {
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	snps,eee-force-disable;
+	status = "okay";
+};
+
+&gmac2 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r1_pins
+			&r1oen_pins>;
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&gmac3 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r2_pins
+			&r2oen_pins>;
+	phy-handle = <&phy1>;
+	status = "okay";
 };
 
 &serial0 {
 	status = "okay";
 };
 
+&fiu0 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@80000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bbuboot1@0 {
+				label = "bb-uboot-1";
+				reg = <0x0000000 0x80000>;
+				read-only;
+				};
+			bbuboot2@80000 {
+				label = "bb-uboot-2";
+				reg = <0x0080000 0x80000>;
+				read-only;
+				};
+			envparam@100000 {
+				label = "env-param";
+				reg = <0x0100000 0x40000>;
+				read-only;
+				};
+			spare@140000 {
+				label = "spare";
+				reg = <0x0140000 0xC0000>;
+				};
+			kernel@200000 {
+				label = "kernel";
+				reg = <0x0200000 0x400000>;
+				};
+			rootfs@600000 {
+				label = "rootfs";
+				reg = <0x0600000 0x700000>;
+				};
+			spare1@D00000 {
+				label = "spare1";
+				reg = <0x0D00000 0x200000>;
+				};
+			spare2@F00000 {
+				label = "spare2";
+				reg = <0x0F00000 0x200000>;
+				};
+			spare3@1100000 {
+				label = "spare3";
+				reg = <0x1100000 0x200000>;
+				};
+			spare4@1300000 {
+				label = "spare4";
+				reg = <0x1300000 0x0>;
+			};
+		};
+	};
+};
+
+&fiu1 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@A0000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi1-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiu3 {
+	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@A0000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi3-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiux {
+	spix-mode;
+};
+
+&sdhci {
+	status = "okay";
+};
+
+&udc0 {
+	status = "okay";
+};
+
+&udc1 {
+	status = "okay";
+};
+
+&udc2 {
+	status = "okay";
+};
+
+&udc3 {
+	status = "okay";
+};
+
+&udc4 {
+	status = "okay";
+};
+
+&udc5 {
+	status = "okay";
+};
+
+&udc6 {
+	status = "okay";
+};
+
+&udc7 {
+	status = "okay";
+};
+
+&mc {
+	status = "okay";
+};
+
+&peci {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc {
+	#io-channel-cells = <1>;
+	status = "okay";
+};
+
 &watchdog1 {
 	status = "okay";
 };
+
+&pwm_fan {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins &pwm1_pins
+		&pwm2_pins &pwm3_pins
+		&pwm4_pins &pwm5_pins
+		&pwm6_pins &pwm7_pins
+		&fanin0_pins &fanin1_pins
+		&fanin2_pins &fanin3_pins
+		&fanin4_pins &fanin5_pins
+		&fanin6_pins &fanin7_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fan@0 {
+		reg = <0x00>;
+		fan-tach-ch = /bits/ 8 <0x00 0x01>;
+		cooling-levels = <127 255>;
+	};
+	fan@1 {
+		reg = <0x01>;
+		fan-tach-ch = /bits/ 8 <0x02 0x03>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@2 {
+		reg = <0x02>;
+		fan-tach-ch = /bits/ 8 <0x04 0x05>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@3 {
+		reg = <0x03>;
+		fan-tach-ch = /bits/ 8 <0x06 0x07>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@4 {
+		reg = <0x04>;
+		fan-tach-ch = /bits/ 8 <0x08 0x09>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@5 {
+		reg = <0x05>;
+		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@6 {
+		reg = <0x06>;
+		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@7 {
+		reg = <0x07>;
+		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+};
+
+&pspi {
+	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	Flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <1000000>;
+		partition@0 {
+			label = "spi1_spare0";
+			reg = <0x0 0x0>;
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	tmp100@48 {
+		compatible = "tmp100";
+		reg = <0x48>;
+		status = "okay";
+	};
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&i2c16 {
+	status = "okay";
+};
+
+&i2c17 {
+	status = "okay";
+};
+
+&i2c18 {
+	status = "okay";
+};
+
+&i2c19 {
+	status = "okay";
+};
+
+&i2c20 {
+	status = "okay";
+};
+
+&i2c21 {
+	status = "okay";
+};
+
+&i2c22 {
+	status = "okay";
+};
+
+&i2c23 {
+	status = "okay";
+};
+
+&i2c24 {
+	status = "okay";
+};
+
+&i2c25 {
+	status = "okay";
+};
+
+&i2c26 {
+	status = "okay";
+};
-- 
2.34.1
Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes
Posted by Krzysztof Kozlowski 2 months, 3 weeks ago 
On 17/07/2025 15:53, Tomer Maimon wrote:
> Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by
> adding device nodes for Ethernet controllers, MMC controller, SPI
> controllers, USB device controllers, random number generator, ADC,
> PWM-FAN controller, I2C controllers, and PECI interface.
> Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and
> aliases for device access.
> This patch enhances functionality for NPCM845-EVB platform.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
>  1 file changed, 445 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> index 2638ee1c3846..46d5bd1c2129 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -10,6 +10,42 @@ / {
>  
>  	aliases {
>  		serial0 = &serial0;
> +		ethernet1 = &gmac1;
> +		ethernet2 = &gmac2;
> +		ethernet3 = &gmac3;
> +		mdio-gpio0 = &mdio0;
> +		mdio-gpio1 = &mdio1;
> +		fiu0 = &fiu0;
> +		fiu1 = &fiu3;
> +		fiu2 = &fiux;
> +		fiu3 = &fiu1;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
> +		i2c8 = &i2c8;
> +		i2c9 = &i2c9;
> +		i2c10 = &i2c10;
> +		i2c11 = &i2c11;
> +		i2c12 = &i2c12;
> +		i2c13 = &i2c13;
> +		i2c14 = &i2c14;
> +		i2c15 = &i2c15;
> +		i2c16 = &i2c16;
> +		i2c17 = &i2c17;
> +		i2c18 = &i2c18;
> +		i2c19 = &i2c19;
> +		i2c20 = &i2c20;
> +		i2c21 = &i2c21;
> +		i2c22 = &i2c22;
> +		i2c23 = &i2c23;
> +		i2c24 = &i2c24;
> +		i2c25 = &i2c25;
> +		i2c26 = &i2c26;
>  	};
>  
>  	chosen {
> @@ -25,12 +61,421 @@ refclk: refclk-25mhz {
>  		clock-frequency = <25000000>;
>  		#clock-cells = <0>;
>  	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tip_reserved: tip@0 {
> +			reg = <0x0 0x0 0x0 0x6200000>;
> +		};
> +	};
> +
> +	mdio0: mdio@0 {

Huh... this should fail checks. It's not MMIO node, is it?


> +		compatible = "virtual,mdio-gpio";

where is the reg?

Please confirm that you introduced no new dtbs_check W=1 warnings.

> +		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
> +			<&gpio1 26 GPIO_ACTIVE_HIGH>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		phy0: ethernet-phy@1 {
> +		};
> +	};
> +

...

> +		reg = <0x05>;
> +		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +	fan@6 {
> +		reg = <0x06>;
> +		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +	fan@7 {
> +		reg = <0x07>;
> +		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +};
> +
> +&pspi {
> +	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +	Flash@0 {

DTS coding style, naming...



Best regards,
Krzysztof
Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes
Posted by Tomer Maimon 2 months, 1 week ago 
Hi Krzysztof,

On Thu, 17 Jul 2025 at 17:25, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 17/07/2025 15:53, Tomer Maimon wrote:
> > Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by
> > adding device nodes for Ethernet controllers, MMC controller, SPI
> > controllers, USB device controllers, random number generator, ADC,
> > PWM-FAN controller, I2C controllers, and PECI interface.
> > Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and
> > aliases for device access.
> > This patch enhances functionality for NPCM845-EVB platform.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
> >  1 file changed, 445 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > index 2638ee1c3846..46d5bd1c2129 100644
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > @@ -10,6 +10,42 @@ / {
> >
> >       aliases {
> >               serial0 = &serial0;
> > +             ethernet1 = &gmac1;
> > +             ethernet2 = &gmac2;
> > +             ethernet3 = &gmac3;
> > +             mdio-gpio0 = &mdio0;
> > +             mdio-gpio1 = &mdio1;
> > +             fiu0 = &fiu0;
> > +             fiu1 = &fiu3;
> > +             fiu2 = &fiux;
> > +             fiu3 = &fiu1;
> > +             i2c0 = &i2c0;
> > +             i2c1 = &i2c1;
> > +             i2c2 = &i2c2;
> > +             i2c3 = &i2c3;
> > +             i2c4 = &i2c4;
> > +             i2c5 = &i2c5;
> > +             i2c6 = &i2c6;
> > +             i2c7 = &i2c7;
> > +             i2c8 = &i2c8;
> > +             i2c9 = &i2c9;
> > +             i2c10 = &i2c10;
> > +             i2c11 = &i2c11;
> > +             i2c12 = &i2c12;
> > +             i2c13 = &i2c13;
> > +             i2c14 = &i2c14;
> > +             i2c15 = &i2c15;
> > +             i2c16 = &i2c16;
> > +             i2c17 = &i2c17;
> > +             i2c18 = &i2c18;
> > +             i2c19 = &i2c19;
> > +             i2c20 = &i2c20;
> > +             i2c21 = &i2c21;
> > +             i2c22 = &i2c22;
> > +             i2c23 = &i2c23;
> > +             i2c24 = &i2c24;
> > +             i2c25 = &i2c25;
> > +             i2c26 = &i2c26;
> >       };
> >
> >       chosen {
> > @@ -25,12 +61,421 @@ refclk: refclk-25mhz {
> >               clock-frequency = <25000000>;
> >               #clock-cells = <0>;
> >       };
> > +
> > +     reserved-memory {
> > +             #address-cells = <2>;
> > +             #size-cells = <2>;
> > +             ranges;
> > +
> > +             tip_reserved: tip@0 {
> > +                     reg = <0x0 0x0 0x0 0x6200000>;
> > +             };
> > +     };
> > +
> > +     mdio0: mdio@0 {
>
> Huh... this should fail checks. It's not MMIO node, is it?
No, it's MDIO node,
https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
Should I modify the node name? If yes, which node name should I use?
>
>
> > +             compatible = "virtual,mdio-gpio";
>
> where is the reg?
It does not include reg in the mother node, but only in the child.
>
> Please confirm that you introduced no new dtbs_check W=1 warnings.
>
> > +             gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
> > +                     <&gpio1 26 GPIO_ACTIVE_HIGH>;
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +
> > +             phy0: ethernet-phy@1 {
> > +             };
> > +     };
> > +
>
> ...
>
> > +             reg = <0x05>;
> > +             fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
> > +             cooling-levels = /bits/ 8 <127 255>;
> > +     };
> > +     fan@6 {
> > +             reg = <0x06>;
> > +             fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
> > +             cooling-levels = /bits/ 8 <127 255>;
> > +     };
> > +     fan@7 {
> > +             reg = <0x07>;
> > +             fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
> > +             cooling-levels = /bits/ 8 <127 255>;
> > +     };
> > +};
> > +
> > +&pspi {
> > +     cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> > +     status = "okay";
> > +     Flash@0 {
>
> DTS coding style, naming...
>
>
>
> Best regards,
> Krzysztof

Thanks,

Tomer
Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes
Posted by Krzysztof Kozlowski 2 months, 1 week ago 
On 28/07/2025 14:12, Tomer Maimon wrote:
>>> +
>>> +     mdio0: mdio@0 {
>>
>> Huh... this should fail checks. It's not MMIO node, is it?
> No, it's MDIO node,
> https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
> Should I modify the node name? If yes, which node name should I use?
>>
>>
>>> +             compatible = "virtual,mdio-gpio";
>>
>> where is the reg?
> It does not include reg in the mother node, but only in the child.

You put the unit address...

>>
>> Please confirm that you introduced no new dtbs_check W=1 warnings.

I need you to answer this.



Best regards,
Krzysztof
Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes
Posted by Tomer Maimon 2 months, 1 week ago 
Hi Krzysztof

On Tue, 29 Jul 2025 at 09:21, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/07/2025 14:12, Tomer Maimon wrote:
> >>> +
> >>> +     mdio0: mdio@0 {
> >>
> >> Huh... this should fail checks. It's not MMIO node, is it?
> > No, it's MDIO node,
> > https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
> > Should I modify the node name? If yes, which node name should I use?
> >>
> >>
> >>> +             compatible = "virtual,mdio-gpio";
> >>
> >> where is the reg?
> > It does not include reg in the mother node, but only in the child.
>
> You put the unit address...
OK
>
> >>
> >> Please confirm that you introduced no new dtbs_check W=1 warnings.
>
> I need you to answer this.
I didn't run dtbs_check with W=1 and the mdio-gpio document. I will
make sure to run dtbs_check W=1 before submitting the next version
>
>
>
> Best regards,
> Krzysztof

Best regards,

Tomer

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