According to PCIe specification, add FMT and TYPE definition
for TLP header. And also add macro to combine FMT and TYPE to
1 byte.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
include/uapi/linux/pci_regs.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index a3a3e942dedf..700b915e00f5 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1230,4 +1230,36 @@
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
+/* Fmt[2:0] encoding for TLP Header */
+#define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data
+#define PCI_TLP_FMT_4DW_NO_DATA 0x1 // 4DW header, no data
+#define PCI_TLP_FMT_3DW_DATA 0x2 // 3DW header, with data
+#define PCI_TLP_FMT_4DW_DATA 0x3 // 4DW header, with data
+#define PCI_TLP_FMT_PREFIX 0x4 // Prefix header
+
+/* Type[4:0] encoding for TLP Header */
+#define PCI_TLP_TYPE_MEM_RD 0x00 // Memory Read Request
+#define PCI_TLP_TYPE_MEM_RDLK 0x01 // Memory Read Lock Request
+#define PCI_TLP_TYPE_MEM_WR 0x00 // Memory Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_IO_RD 0x02 // IO Read Request
+#define PCI_TLP_TYPE_IO_WR 0x02 // IO Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_CFG0_RD 0x04 // Config Type 0 Read Request
+#define PCI_TLP_TYPE_CFG0_WR 0x04 // Config Type 0 Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_CFG1_RD 0x05 // Config Type 1 Read Request
+#define PCI_TLP_TYPE_CFG1_WR 0x05 // Config Type 1 Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_MSG 0x10 // Message Request (see routing field)
+#define PCI_TLP_TYPE_MSGD 0x11 // Message Request with Data (see routing field)
+#define PCI_TLP_TYPE_CPL 0x0A // Completion without Data
+#define PCI_TLP_TYPE_CPLD 0x0A // Completion with Data (Fmt must be with data)
+#define PCI_TLP_TYPE_CPLLCK 0x0B // Completion Locked
+#define PCI_TLP_TYPE_CPLDLCK 0x0B // Completion with Data Locked (Fmt must be with data)
+#define PCI_TLP_TYPE_FETCH_ADD 0x0C // Fetch and Add AtomicOp Request
+#define PCI_TLP_TYPE_SWAP 0x0D // Unconditional Swap AtomicOp Request
+#define PCI_TLP_TYPE_CMP_SWAP 0x0E // Compare and Swap AtomicOp Request
+#define PCI_TLP_TYPE_LOCAL_PREFIX 0x00 // Local TLP Prefix (Fmt = 0x4)
+#define PCI_TLP_TYPE_E2E_PREFIX 0x10 // End-to-End TLP Prefix (Fmt = 0x4)
+
+/* Macro to combine Fmt and Type into the 8-bit field */
+#define PCIE_TLP_FMT_TYPE(fmt, type) (((fmt) << 5) | ((type) & 0x1F))
+
#endif /* LINUX_PCI_REGS_H */
--
2.43.0Hi Jacky,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus robh/for-next linusw-pinctrl/devel linusw-pinctrl/for-next linus/master v6.16-rc6 next-20250715]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jacky-Chou/dt-bindings-soc-aspeed-Add-ASPEED-PCIe-Config-support/20250715-114814
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20250715034320.2553837-9-jacky_chou%40aspeedtech.com
patch subject: [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header
config: i386-buildonly-randconfig-004-20250715 (https://download.01.org/0day-ci/archive/20250716/202507160314.e3odwyX7-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250716/202507160314.e3odwyX7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202507160314.e3odwyX7-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from <built-in>:1:
In file included from ./usr/include/linux/pci.h:21:
>> usr/include/linux/pci_regs.h:1234:39: warning: // comments are not allowed in this language [-Wcomment]
1234 | #define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data
| ^
1 warning generated.
--
In file included from <built-in>:1:
>> ./usr/include/linux/pci_regs.h:1234:39: warning: // comments are not allowed in this language [-Wcomment]
1234 | #define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data
| ^
1 warning generated.
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Tue, Jul 15, 2025 at 11:43:18AM +0800, Jacky Chou wrote: > According to PCIe specification, add FMT and TYPE definition > for TLP header. And also add macro to combine FMT and TYPE to > 1 byte. > > Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> > --- > include/uapi/linux/pci_regs.h | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) I don't think these definitions are relevant to uapi users, so they could go in drivers/pci/pci.h, similar to the existing PCIE_MSG_* definitions. Please follow the style of PCIE_MSG_*, including the brief spec citations and /* */ comments. Not sure we need *all* of these; it looks like you only use: PCI_TLP_TYPE_CFG0_RD PCI_TLP_TYPE_CFG0_WR PCI_TLP_TYPE_CFG1_RD PCI_TLP_TYPE_CFG1_WR PCI_TLP_FMT_3DW_NO_DATA PCI_TLP_FMT_3DW_DATA > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index a3a3e942dedf..700b915e00f5 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1230,4 +1230,36 @@ > #define PCI_DVSEC_CXL_PORT_CTL 0x0c > #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 > > +/* Fmt[2:0] encoding for TLP Header */ > +#define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data > +#define PCI_TLP_FMT_4DW_NO_DATA 0x1 // 4DW header, no data > +#define PCI_TLP_FMT_3DW_DATA 0x2 // 3DW header, with data > +#define PCI_TLP_FMT_4DW_DATA 0x3 // 4DW header, with data > +#define PCI_TLP_FMT_PREFIX 0x4 // Prefix header > + > +/* Type[4:0] encoding for TLP Header */ > +#define PCI_TLP_TYPE_MEM_RD 0x00 // Memory Read Request > +#define PCI_TLP_TYPE_MEM_RDLK 0x01 // Memory Read Lock Request > +#define PCI_TLP_TYPE_MEM_WR 0x00 // Memory Write Request (Fmt must be with data) > +#define PCI_TLP_TYPE_IO_RD 0x02 // IO Read Request > +#define PCI_TLP_TYPE_IO_WR 0x02 // IO Write Request (Fmt must be with data) > +#define PCI_TLP_TYPE_CFG0_RD 0x04 // Config Type 0 Read Request > +#define PCI_TLP_TYPE_CFG0_WR 0x04 // Config Type 0 Write Request (Fmt must be with data) > +#define PCI_TLP_TYPE_CFG1_RD 0x05 // Config Type 1 Read Request > +#define PCI_TLP_TYPE_CFG1_WR 0x05 // Config Type 1 Write Request (Fmt must be with data) > +#define PCI_TLP_TYPE_MSG 0x10 // Message Request (see routing field) > +#define PCI_TLP_TYPE_MSGD 0x11 // Message Request with Data (see routing field) > +#define PCI_TLP_TYPE_CPL 0x0A // Completion without Data > +#define PCI_TLP_TYPE_CPLD 0x0A // Completion with Data (Fmt must be with data) > +#define PCI_TLP_TYPE_CPLLCK 0x0B // Completion Locked > +#define PCI_TLP_TYPE_CPLDLCK 0x0B // Completion with Data Locked (Fmt must be with data) > +#define PCI_TLP_TYPE_FETCH_ADD 0x0C // Fetch and Add AtomicOp Request > +#define PCI_TLP_TYPE_SWAP 0x0D // Unconditional Swap AtomicOp Request > +#define PCI_TLP_TYPE_CMP_SWAP 0x0E // Compare and Swap AtomicOp Request > +#define PCI_TLP_TYPE_LOCAL_PREFIX 0x00 // Local TLP Prefix (Fmt = 0x4) > +#define PCI_TLP_TYPE_E2E_PREFIX 0x10 // End-to-End TLP Prefix (Fmt = 0x4) > + > +/* Macro to combine Fmt and Type into the 8-bit field */ > +#define PCIE_TLP_FMT_TYPE(fmt, type) (((fmt) << 5) | ((type) & 0x1F)) This looks like it might be controller-specific and could go in pcie-aspeed.c.
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