Add Epoch subsystem (EPSS) L3 scaling support on QCS8300 SoC.

Changes since v1:
 - Removed SoC specific compatible "qcom,qcs8300-epss-l3"
   from driver and used SA8775P SoC compatible as fallback in devicetree.
 - As the EPSS hardware in QCS8300 and SA8775P SoCs are same, a 
   family-specific compatible string for the SA8775P has been added to the
   bindings. This avoids the need to explicitly listing each SoC in the
   match table and the family-specific fallback compatible can be used 
   for SoCs sharing the same hardware.
 - As suggested by konrad, added EPSS path handles for CPU nodes.

Imran Shaik (1):
  arm64: dts: qcom: qcs8300: Add CPU OPP tables to scale DDR/L3

Raviteja Laggyshetty (2):
  dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
  arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node

 .../bindings/interconnect/qcom,osm-l3.yaml    |   5 +
 arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 301 ++++++++++++++++++
 2 files changed, 306 insertions(+)

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2.43.0