From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
platforms. The GCR.U memory region contains shadow copies of the RISC-V
mtime register and the hrtime Global Configuration Register.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/timer/mti,gcru.yaml        | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/mti,gcru.yaml b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ceaf90bad5332b64f3c1f28bebdc28d78443898a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/mti,gcru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GCR.U timer device for RISC-V platforms
+
+maintainers:
+  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
+
+description:
+  The GCR.U memory region contains memory mapped shadow copies of
+  mtime and hrtime Global Configuration Registers,
+  which software can choose to make accessible from user mode.
+
+properties:
+  compatible:
+    const: mti,gcru
+
+  reg:
+    items:
+      - description: Read-only shadow copy of the RISC-V mtime register.
+      - description: Read-only shadow copy of the high resolution timer register.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    timer@1617f000 {
+        compatible = "mti,gcru";
+        reg = <0x1617f050 0x8>,
+              <0x1617f090 0x8>;
+    };

-- 
2.34.1

On Fri, Jul 11, 2025 at 11:56:45PM +0200, Aleksa Paunovic wrote:
> +$id: http://devicetree.org/schemas/timer/mti,gcru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: GCR.U timer device for RISC-V platforms
> +
> +maintainers:
> +  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> +
> +description:
> +  The GCR.U memory region contains memory mapped shadow copies of
> +  mtime and hrtime Global Configuration Registers,
> +  which software can choose to make accessible from user mode.
> +
> +properties:
> +  compatible:
> +    const: mti,gcru

Is this architecture? vendor prefix suggests not. So is this for SoC?
Then why there are no SoC compatibles here instead?

Best regards,
Krzysztof

On 7/14/25 09:24, Krzysztof Kozlowski wrote:

> On Fri, Jul 11, 2025 at 11:56:45PM +0200, Aleksa Paunovic wrote:
>> +$id: http://devicetree.org/schemas/timer/mti,gcru.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: GCR.U timer device for RISC-V platforms
>> +
>> +maintainers:
>> +  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> +
>> +description:
>> +  The GCR.U memory region contains memory mapped shadow copies of
>> +  mtime and hrtime Global Configuration Registers,
>> +  which software can choose to make accessible from user mode.
>> +
>> +properties:
>> +  compatible:
>> +    const: mti,gcru
> Is this architecture? vendor prefix suggests not. So is this for SoC?
> Then why there are no SoC compatibles here instead?
Hi Krzysztof,

Thank you for your comment.
You are right, this is for the MIPS P8700 SoC. Will fix this in v6.


Best regards,

Aleksa

>
> Best regards,
> Krzysztof