Initialize the APIC ID in the Secure AVIC APIC backing page with
the APIC_ID msr value read from Hypervisor. CPU topology evaluation
later during boot would catch and report any duplicate APIC ID for
two CPUs.

Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
---
Changes since v7:
 - No change.

 arch/x86/kernel/apic/x2apic_savic.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index 186e69a5e169..618643e7242f 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -131,6 +131,18 @@ static void savic_write(u32 reg, u32 data)
 	}
 }
 
+static void init_apic_page(struct apic_page *ap)
+{
+	u32 apic_id;
+
+	/*
+	 * Before Secure AVIC is enabled, APIC msr reads are intercepted.
+	 * APIC_ID msr read returns the value from the Hypervisor.
+	 */
+	apic_id = native_apic_msr_read(APIC_ID);
+	apic_set_reg(ap, APIC_ID, apic_id);
+}
+
 static void savic_setup(void)
 {
 	void *backing_page;
@@ -138,6 +150,7 @@ static void savic_setup(void)
 	unsigned long gpa;
 
 	backing_page = this_cpu_ptr(apic_page);
+	init_apic_page(backing_page);
 	gpa = __pa(backing_page);
 
 	/*
-- 
2.34.1

On Wed, Jul 9, 2025 at 11:40 AM Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> wrote:
>
> Initialize the APIC ID in the Secure AVIC APIC backing page with
> the APIC_ID msr value read from Hypervisor. CPU topology evaluation
> later during boot would catch and report any duplicate APIC ID for
> two CPUs.
>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
> ---
> Changes since v7:
>  - No change.
>

Reviewed-by: Tianyu Lan <tiala@microsoft.com>

>  arch/x86/kernel/apic/x2apic_savic.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
> index 186e69a5e169..618643e7242f 100644
> --- a/arch/x86/kernel/apic/x2apic_savic.c
> +++ b/arch/x86/kernel/apic/x2apic_savic.c
> @@ -131,6 +131,18 @@ static void savic_write(u32 reg, u32 data)
>         }
>  }
>
> +static void init_apic_page(struct apic_page *ap)
> +{
> +       u32 apic_id;
> +
> +       /*
> +        * Before Secure AVIC is enabled, APIC msr reads are intercepted.
> +        * APIC_ID msr read returns the value from the Hypervisor.
> +        */
> +       apic_id = native_apic_msr_read(APIC_ID);
> +       apic_set_reg(ap, APIC_ID, apic_id);
> +}
> +
>  static void savic_setup(void)
>  {
>         void *backing_page;
> @@ -138,6 +150,7 @@ static void savic_setup(void)
>         unsigned long gpa;
>
>         backing_page = this_cpu_ptr(apic_page);
> +       init_apic_page(backing_page);
>         gpa = __pa(backing_page);
>
>         /*
> --
> 2.34.1
>
>


-- 
Thanks
Tianyu Lan