The ROCK 2A and ROCK 2F is a high-performance single board computer
developed by Radxa, based on the Rockchip RK3528A SoC.
Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Schematics:
- https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf
- https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf
---
arch/arm64/boot/dts/rockchip/Makefile | 2 +
.../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++
.../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++
.../boot/dts/rockchip/rk3528-rock-2f.dts | 10 +
4 files changed, 386 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index e43565c53c56..d0d21f5029ea 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -90,6 +90,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
new file mode 100644
index 000000000000..fc23c51836b1
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3528.dtsi"
+
+/ {
+ aliases {
+ i2c1 = &i2c1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "MASKROM";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_led_b>;
+
+ led-state {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vdd_0v9: regulator-0v9-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: regulator-1v1-vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc_3v3: regulator-3v3-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_wifi: regulator-3v3-vcc-wifi {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_wifi_pwr>;
+ regulator-name = "vcc_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb20: regulator-5v0-vcc-usb20 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_en>;
+ regulator-name = "vcc5v0_usb20";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vccio_sd: regulator-vccio-sd {
+ compatible = "regulator-gpio";
+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_vol_ctrl_h>;
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x0>, <3300000 0x1>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_arm: regulator-vdd-arm {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <746000>;
+ regulator-max-microvolt = <1201000>;
+ regulator-settling-time-up-us = <250>;
+ };
+
+ vdd_logic: regulator-vdd-logic {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc5v0_sys>;
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <705000>;
+ regulator-max-microvolt = <1006000>;
+ regulator-settling-time-up-us = <250>;
+ };
+
+ rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-wlan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v3>;
+ };
+};
+
+&pinctrl {
+ bluetooth {
+ bt_wake_host_h: bt-wake-host-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ host_wake_bt_h: host-wake-bt-h {
+ rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ state_led_b: state-led-b {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_en: usb-host-en {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ usb_wifi_pwr: usb-wifi-pwr {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_wake_host_h: wifi-wake-host-h {
+ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1m0_pins>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
new file mode 100644
index 000000000000..c6f4d9b683d8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3528-rock-2.dtsi"
+
+/ {
+ model = "Radxa ROCK 2A";
+ compatible = "radxa,rock-2a", "rockchip,rk3528";
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_en>;
+ regulator-name = "vcc5v0_usb30_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
+ status = "okay";
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_led_b>, <&sys_led_g>;
+
+ led-sys {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+};
+
+&mdio1 {
+ rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn_l>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ gmac1_rstn_l: gmac1-rstn-l {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ sys_led_g: sys-led-g {
+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_otg_en: usb-otg-en {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
new file mode 100644
index 000000000000..3e2b9b685cb2
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3528-rock-2.dtsi"
+
+/ {
+ model = "Radxa ROCK 2F";
+ compatible = "radxa,rock-2f", "rockchip,rk3528";
+};
--
2.49.0On Tue, Jul 08, 2025 at 10:48:52PM +0000, Jonas Karlman wrote: > The ROCK 2A and ROCK 2F is a high-performance single board computer > developed by Radxa, based on the Rockchip RK3528A SoC. > > Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- > Schematics: > - https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf > - https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf > --- > arch/arm64/boot/dts/rockchip/Makefile | 2 + > .../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++ > .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++ > .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 + > 4 files changed, 386 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts While testing the patch on my Rock 2A board, I noticed one of my SDcard that works perfectly on Radxa E20C and NanoPi Zero 2 cannot be correctly read out under UHS-125-SDR mode, # dd if=/dev/mmcblk1 of=/dev/null bs=4M count=4 [ 18.616828] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) [ 19.193315] mmc1: Skipping voltage switch [ 19.202046] mmc1: tried to HW reset card, got error -110 [ 19.213312] mmcblk1: recovery failed! [ 19.213709] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 256 prio class 0 [ 19.225201] mmcblk1: recovery failed! [ 19.225530] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0 [ 19.226283] Buffer I/O error on dev mmcblk1, logical block 0, async page read dd: /dev/mmcblk1: I/O error which could be reproduced stably. the SDMMC controller issued interesting messages during the tuning process, [ 0.665246] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) [ 0.851940] dwmmc_rockchip ffc30000.mmc: All phases work, using default phase 90. but actually it doesn't work with phase = 90. If the frequency is limited to 100MHz with max-frequency = <100000000> instead of the default 150MHz, tuning results in a very different phase, [ 0.665483] mmc_host mmc1: Bus speed (slot 0) = 99600000Hz (slot req 100000000Hz, actual 99600000HZ div = 0) [ 1.166340] dwmmc_rockchip ffc30000.mmc: Successfully tuned phase to 141 and the card works, too. If I set rockchip,default-sample-phase to 141 in devicetree, the card could work at full 150MHz as well. I think there's something wrong with the tuning process, or the board's design cannot always run reliably at 150MHz. Could you reproduce similar failures on Radxa 2A? If so, it may be necessary to lower the SDMMC's maximum frequency for the board. Regards, Yao Zi
On Wed, 09 Jul 2025 04:25:34 +0000, Yao Zi wrote: > On Tue, Jul 08, 2025 at 10:48:52PM +0000, Jonas Karlman wrote: > > The ROCK 2A and ROCK 2F is a high-performance single board computer > > developed by Radxa, based on the Rockchip RK3528A SoC. > > > > Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards. > > > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > > --- > > Schematics: > > - https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf > > - https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf > > --- > > arch/arm64/boot/dts/rockchip/Makefile | 2 + > > .../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++ > > .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++ > > .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 + > > 4 files changed, 386 insertions(+) > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts > > While testing the patch on my Rock 2A board, I noticed one of my SDcard > that works perfectly on Radxa E20C and NanoPi Zero 2 cannot be correctly > read out under UHS-125-SDR mode, > > # dd if=/dev/mmcblk1 of=/dev/null bs=4M count=4 > [ 18.616828] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 19.193315] mmc1: Skipping voltage switch > [ 19.202046] mmc1: tried to HW reset card, got error -110 > [ 19.213312] mmcblk1: recovery failed! > [ 19.213709] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 256 prio class 0 > [ 19.225201] mmcblk1: recovery failed! > [ 19.225530] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0 > [ 19.226283] Buffer I/O error on dev mmcblk1, logical block 0, async page read > dd: /dev/mmcblk1: I/O error > > which could be reproduced stably. > > the SDMMC controller issued interesting messages during the tuning > process, > > [ 0.665246] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) > [ 0.851940] dwmmc_rockchip ffc30000.mmc: All phases work, using default phase 90. > > but actually it doesn't work with phase = 90. If the frequency is > limited to 100MHz with max-frequency = <100000000> instead of the > default 150MHz, tuning results in a very different phase, > > [ 0.665483] mmc_host mmc1: Bus speed (slot 0) = 99600000Hz (slot req 100000000Hz, actual 99600000HZ div = 0) > [ 1.166340] dwmmc_rockchip ffc30000.mmc: Successfully tuned phase to 141 > > and the card works, too. If I set rockchip,default-sample-phase to 141 > in devicetree, the card could work at full 150MHz as well. > > I think there's something wrong with the tuning process, or the board's > design cannot always run reliably at 150MHz. > > Could you reproduce similar failures on Radxa 2A? If so, it may be > necessary to lower the SDMMC's maximum frequency for the board. > > Regards, > Yao Zi > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: attempting to guess base-commit... Base: tags/v6.16-rc1-34-g7f9509791507 (exact match) If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/rockchip/' for aG3vPsUd-FPkhi-S@pie.lan: arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dtb: /soc/power-management@ff600000: failed to match any schema with compatible: ['rockchip,rk3528-pmu', 'syscon', 'simple-mfd'] arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dtb: /soc/power-management@ff600000/power-controller: failed to match any schema with compatible: ['rockchip,rk3528-power-controller'] arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dtb: gpu@ff700000 (rockchip,rk3528-mali): compatible: 'oneOf' conditional failed, one must be fixed: ['rockchip,rk3528-mali', 'arm,mali-450'] is too short 'allwinner,sun8i-a23-mali' was expected 'rockchip,rk3528-mali' is not one of ['allwinner,sun4i-a10-mali', 'allwinner,sun7i-a20-mali', 'allwinner,sun8i-h3-mali', 'allwinner,sun8i-r40-mali', 'allwinner,sun50i-a64-mali', 'rockchip,rk3036-mali', 'rockchip,rk3066-mali', 'rockchip,rk3128-mali', 'rockchip,rk3188-mali', 'rockchip,rk3228-mali', 'samsung,exynos4210-mali', 'st,stih410-mali', 'stericsson,db8500-mali', 'xlnx,zynqmp-mali'] 'rockchip,rk3528-mali' is not one of ['allwinner,sun50i-h5-mali', 'amlogic,meson8-mali', 'amlogic,meson8b-mali', 'amlogic,meson-gxbb-mali', 'amlogic,meson-gxl-mali', 'hisilicon,hi6220-mali', 'mediatek,mt7623-mali', 'rockchip,rk3328-mali'] 'allwinner,sun7i-a20-mali' was expected 'arm,mali-400' was expected from schema $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dtb: /soc/gpu@ff700000: failed to match any schema with compatible: ['rockchip,rk3528-mali', 'arm,mali-450'] arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dtb: /soc/power-management@ff600000: failed to match any schema with compatible: ['rockchip,rk3528-pmu', 'syscon', 'simple-mfd'] arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dtb: /soc/power-management@ff600000/power-controller: failed to match any schema with compatible: ['rockchip,rk3528-power-controller'] arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dtb: gpu@ff700000 (rockchip,rk3528-mali): compatible: 'oneOf' conditional failed, one must be fixed: ['rockchip,rk3528-mali', 'arm,mali-450'] is too short 'allwinner,sun8i-a23-mali' was expected 'rockchip,rk3528-mali' is not one of ['allwinner,sun4i-a10-mali', 'allwinner,sun7i-a20-mali', 'allwinner,sun8i-h3-mali', 'allwinner,sun8i-r40-mali', 'allwinner,sun50i-a64-mali', 'rockchip,rk3036-mali', 'rockchip,rk3066-mali', 'rockchip,rk3128-mali', 'rockchip,rk3188-mali', 'rockchip,rk3228-mali', 'samsung,exynos4210-mali', 'st,stih410-mali', 'stericsson,db8500-mali', 'xlnx,zynqmp-mali'] 'rockchip,rk3528-mali' is not one of ['allwinner,sun50i-h5-mali', 'amlogic,meson8-mali', 'amlogic,meson8b-mali', 'amlogic,meson-gxbb-mali', 'amlogic,meson-gxl-mali', 'hisilicon,hi6220-mali', 'mediatek,mt7623-mali', 'rockchip,rk3328-mali'] 'allwinner,sun7i-a20-mali' was expected 'arm,mali-400' was expected from schema $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dtb: /soc/gpu@ff700000: failed to match any schema with compatible: ['rockchip,rk3528-mali', 'arm,mali-450'] arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dtb: /soc/power-management@ff600000: failed to match any schema with compatible: ['rockchip,rk3528-pmu', 'syscon', 'simple-mfd'] arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dtb: /soc/power-management@ff600000/power-controller: failed to match any schema with compatible: ['rockchip,rk3528-power-controller'] arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dtb: gpu@ff700000 (rockchip,rk3528-mali): compatible: 'oneOf' conditional failed, one must be fixed: ['rockchip,rk3528-mali', 'arm,mali-450'] is too short 'allwinner,sun8i-a23-mali' was expected 'rockchip,rk3528-mali' is not one of ['allwinner,sun4i-a10-mali', 'allwinner,sun7i-a20-mali', 'allwinner,sun8i-h3-mali', 'allwinner,sun8i-r40-mali', 'allwinner,sun50i-a64-mali', 'rockchip,rk3036-mali', 'rockchip,rk3066-mali', 'rockchip,rk3128-mali', 'rockchip,rk3188-mali', 'rockchip,rk3228-mali', 'samsung,exynos4210-mali', 'st,stih410-mali', 'stericsson,db8500-mali', 'xlnx,zynqmp-mali'] 'rockchip,rk3528-mali' is not one of ['allwinner,sun50i-h5-mali', 'amlogic,meson8-mali', 'amlogic,meson8b-mali', 'amlogic,meson-gxbb-mali', 'amlogic,meson-gxl-mali', 'hisilicon,hi6220-mali', 'mediatek,mt7623-mali', 'rockchip,rk3328-mali'] 'allwinner,sun7i-a20-mali' was expected 'arm,mali-400' was expected from schema $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dtb: /soc/gpu@ff700000: failed to match any schema with compatible: ['rockchip,rk3528-mali', 'arm,mali-450'] arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dtb: /soc/power-management@ff600000: failed to match any schema with compatible: ['rockchip,rk3528-pmu', 'syscon', 'simple-mfd'] arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dtb: /soc/power-management@ff600000/power-controller: failed to match any schema with compatible: ['rockchip,rk3528-power-controller'] arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dtb: gpu@ff700000 (rockchip,rk3528-mali): compatible: 'oneOf' conditional failed, one must be fixed: ['rockchip,rk3528-mali', 'arm,mali-450'] is too short 'allwinner,sun8i-a23-mali' was expected 'rockchip,rk3528-mali' is not one of ['allwinner,sun4i-a10-mali', 'allwinner,sun7i-a20-mali', 'allwinner,sun8i-h3-mali', 'allwinner,sun8i-r40-mali', 'allwinner,sun50i-a64-mali', 'rockchip,rk3036-mali', 'rockchip,rk3066-mali', 'rockchip,rk3128-mali', 'rockchip,rk3188-mali', 'rockchip,rk3228-mali', 'samsung,exynos4210-mali', 'st,stih410-mali', 'stericsson,db8500-mali', 'xlnx,zynqmp-mali'] 'rockchip,rk3528-mali' is not one of ['allwinner,sun50i-h5-mali', 'amlogic,meson8-mali', 'amlogic,meson8b-mali', 'amlogic,meson-gxbb-mali', 'amlogic,meson-gxl-mali', 'hisilicon,hi6220-mali', 'mediatek,mt7623-mali', 'rockchip,rk3328-mali'] 'allwinner,sun7i-a20-mali' was expected 'arm,mali-400' was expected from schema $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dtb: /soc/gpu@ff700000: failed to match any schema with compatible: ['rockchip,rk3528-mali', 'arm,mali-450']
Hi,
On 7/9/2025 6:25 AM, Yao Zi wrote:
> On Tue, Jul 08, 2025 at 10:48:52PM +0000, Jonas Karlman wrote:
>> The ROCK 2A and ROCK 2F is a high-performance single board computer
>> developed by Radxa, based on the Rockchip RK3528A SoC.
>>
>> Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> ---
>> Schematics:
>> - https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf
>> - https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf
>> ---
>> arch/arm64/boot/dts/rockchip/Makefile | 2 +
>> .../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++
>> .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++
>> .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 +
>> 4 files changed, 386 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
>
> While testing the patch on my Rock 2A board, I noticed one of my SDcard
> that works perfectly on Radxa E20C and NanoPi Zero 2 cannot be correctly
> read out under UHS-125-SDR mode,
>
> # dd if=/dev/mmcblk1 of=/dev/null bs=4M count=4
> [ 18.616828] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
> [ 19.193315] mmc1: Skipping voltage switch
> [ 19.202046] mmc1: tried to HW reset card, got error -110
> [ 19.213312] mmcblk1: recovery failed!
> [ 19.213709] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 256 prio class 0
> [ 19.225201] mmcblk1: recovery failed!
> [ 19.225530] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
> [ 19.226283] Buffer I/O error on dev mmcblk1, logical block 0, async page read
> dd: /dev/mmcblk1: I/O error
>
> which could be reproduced stably.
>
> the SDMMC controller issued interesting messages during the tuning
> process,
>
> [ 0.665246] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0)
> [ 0.851940] dwmmc_rockchip ffc30000.mmc: All phases work, using default phase 90.
>
> but actually it doesn't work with phase = 90. If the frequency is
> limited to 100MHz with max-frequency = <100000000> instead of the
> default 150MHz, tuning results in a very different phase,
>
> [ 0.665483] mmc_host mmc1: Bus speed (slot 0) = 99600000Hz (slot req 100000000Hz, actual 99600000HZ div = 0)
> [ 1.166340] dwmmc_rockchip ffc30000.mmc: Successfully tuned phase to 141
>
> and the card works, too. If I set rockchip,default-sample-phase to 141
> in devicetree, the card could work at full 150MHz as well.
>
> I think there's something wrong with the tuning process, or the board's
> design cannot always run reliably at 150MHz.
>
> Could you reproduce similar failures on Radxa 2A? If so, it may be
> necessary to lower the SDMMC's maximum frequency for the board.
I have not been able to reproduce this issue on any of my ROCK 2A or 2F
boards, my boards seem to tune phase to around 250-265 for the sd-cards
I tested.
Could you try with something like this:
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
index fc23c51836b15..a82791db55699 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
@@ -285,6 +285,10 @@
status = "okay";
};
+&sdmmc_clk {
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
Changing clk drive strength seem to be something that has been done in
Radxa vendor kernel [1], could be something that we can include if it
fixes your issue.
The kernel I tested was built from [2].
[1] https://github.com/radxa/kernel/commit/e9b33cbc97a902560d3f3b43b4d36a1a0ac68a50
[2] https://github.com/Kwiboo/linux-rockchip/commits/next-20250708-rk3528-boards/
Regards,
Jonas
>
> Regards,
> Yao Zi
On Thu, Jul 10, 2025 at 01:56:02AM +0200, Jonas Karlman wrote:
> Hi,
>
> On 7/9/2025 6:25 AM, Yao Zi wrote:
> > On Tue, Jul 08, 2025 at 10:48:52PM +0000, Jonas Karlman wrote:
> >> The ROCK 2A and ROCK 2F is a high-performance single board computer
> >> developed by Radxa, based on the Rockchip RK3528A SoC.
> >>
> >> Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
> >>
> >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> >> ---
> >> Schematics:
> >> - https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf
> >> - https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf
> >> ---
> >> arch/arm64/boot/dts/rockchip/Makefile | 2 +
> >> .../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++
> >> .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++
> >> .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 +
> >> 4 files changed, 386 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
> >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
> >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
> >
> > While testing the patch on my Rock 2A board, I noticed one of my SDcard
> > that works perfectly on Radxa E20C and NanoPi Zero 2 cannot be correctly
> > read out under UHS-125-SDR mode,
> >
> > # dd if=/dev/mmcblk1 of=/dev/null bs=4M count=4
> > [ 18.616828] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
> > [ 19.193315] mmc1: Skipping voltage switch
> > [ 19.202046] mmc1: tried to HW reset card, got error -110
> > [ 19.213312] mmcblk1: recovery failed!
> > [ 19.213709] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 256 prio class 0
> > [ 19.225201] mmcblk1: recovery failed!
> > [ 19.225530] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
> > [ 19.226283] Buffer I/O error on dev mmcblk1, logical block 0, async page read
> > dd: /dev/mmcblk1: I/O error
> >
> > which could be reproduced stably.
> >
> > the SDMMC controller issued interesting messages during the tuning
> > process,
> >
> > [ 0.665246] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0)
> > [ 0.851940] dwmmc_rockchip ffc30000.mmc: All phases work, using default phase 90.
> >
> > but actually it doesn't work with phase = 90. If the frequency is
> > limited to 100MHz with max-frequency = <100000000> instead of the
> > default 150MHz, tuning results in a very different phase,
> >
> > [ 0.665483] mmc_host mmc1: Bus speed (slot 0) = 99600000Hz (slot req 100000000Hz, actual 99600000HZ div = 0)
> > [ 1.166340] dwmmc_rockchip ffc30000.mmc: Successfully tuned phase to 141
> >
> > and the card works, too. If I set rockchip,default-sample-phase to 141
> > in devicetree, the card could work at full 150MHz as well.
> >
> > I think there's something wrong with the tuning process, or the board's
> > design cannot always run reliably at 150MHz.
> >
> > Could you reproduce similar failures on Radxa 2A? If so, it may be
> > necessary to lower the SDMMC's maximum frequency for the board.
>
> I have not been able to reproduce this issue on any of my ROCK 2A or 2F
> boards, my boards seem to tune phase to around 250-265 for the sd-cards
> I tested.
>
> Could you try with something like this:
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
> index fc23c51836b15..a82791db55699 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
> @@ -285,6 +285,10 @@
> status = "okay";
> };
>
> +&sdmmc_clk {
> + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0m0_xfer>;
>
>
> Changing clk drive strength seem to be something that has been done in
> Radxa vendor kernel [1], could be something that we can include if it
> fixes your issue.
This seems to improve the situation a little, but doesn't solve the
issue. Among more than ten times of testing, the tuning process only
worked twice.
> The kernel I tested was built from [2].
I've tried this branch as well, but things don't improve.
Do you consider lower the clock-frequency acceptable?
> [1] https://github.com/radxa/kernel/commit/e9b33cbc97a902560d3f3b43b4d36a1a0ac68a50
> [2] https://github.com/Kwiboo/linux-rockchip/commits/next-20250708-rk3528-boards/
>
> Regards,
> Jonas
>
> >
> > Regards,
> > Yao Zi
>
Regards,
Yao Zi
On 7/10/2025 6:41 PM, Yao Zi wrote:
> On Thu, Jul 10, 2025 at 01:56:02AM +0200, Jonas Karlman wrote:
>> Hi,
>>
>> On 7/9/2025 6:25 AM, Yao Zi wrote:
>>> On Tue, Jul 08, 2025 at 10:48:52PM +0000, Jonas Karlman wrote:
>>>> The ROCK 2A and ROCK 2F is a high-performance single board computer
>>>> developed by Radxa, based on the Rockchip RK3528A SoC.
>>>>
>>>> Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
>>>>
>>>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>>>> ---
>>>> Schematics:
>>>> - https://dl.radxa.com/rock2/2a/v1.2/radxa_rock_2a_v1.2_schematic.pdf
>>>> - https://dl.radxa.com/rock2/2f/radxa_rock2f_v1.01_schematic.pdf
>>>> ---
>>>> arch/arm64/boot/dts/rockchip/Makefile | 2 +
>>>> .../boot/dts/rockchip/rk3528-rock-2.dtsi | 292 ++++++++++++++++++
>>>> .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++
>>>> .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 +
>>>> 4 files changed, 386 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
>>>> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
>>>
>>> While testing the patch on my Rock 2A board, I noticed one of my SDcard
>>> that works perfectly on Radxa E20C and NanoPi Zero 2 cannot be correctly
>>> read out under UHS-125-SDR mode,
>>>
>>> # dd if=/dev/mmcblk1 of=/dev/null bs=4M count=4
>>> [ 18.616828] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
>>> [ 19.193315] mmc1: Skipping voltage switch
>>> [ 19.202046] mmc1: tried to HW reset card, got error -110
>>> [ 19.213312] mmcblk1: recovery failed!
>>> [ 19.213709] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x80700 phys_seg 256 prio class 0
>>> [ 19.225201] mmcblk1: recovery failed!
>>> [ 19.225530] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
>>> [ 19.226283] Buffer I/O error on dev mmcblk1, logical block 0, async page read
>>> dd: /dev/mmcblk1: I/O error
>>>
>>> which could be reproduced stably.
>>>
>>> the SDMMC controller issued interesting messages during the tuning
>>> process,
>>>
>>> [ 0.665246] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0)
>>> [ 0.851940] dwmmc_rockchip ffc30000.mmc: All phases work, using default phase 90.
>>>
>>> but actually it doesn't work with phase = 90. If the frequency is
>>> limited to 100MHz with max-frequency = <100000000> instead of the
>>> default 150MHz, tuning results in a very different phase,
>>>
>>> [ 0.665483] mmc_host mmc1: Bus speed (slot 0) = 99600000Hz (slot req 100000000Hz, actual 99600000HZ div = 0)
>>> [ 1.166340] dwmmc_rockchip ffc30000.mmc: Successfully tuned phase to 141
>>>
>>> and the card works, too. If I set rockchip,default-sample-phase to 141
>>> in devicetree, the card could work at full 150MHz as well.
>>>
>>> I think there's something wrong with the tuning process, or the board's
>>> design cannot always run reliably at 150MHz.
>>>
>>> Could you reproduce similar failures on Radxa 2A? If so, it may be
>>> necessary to lower the SDMMC's maximum frequency for the board.
>>
>> I have not been able to reproduce this issue on any of my ROCK 2A or 2F
>> boards, my boards seem to tune phase to around 250-265 for the sd-cards
>> I tested.
>>
>> Could you try with something like this:
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
>> index fc23c51836b15..a82791db55699 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
>> @@ -285,6 +285,10 @@
>> status = "okay";
>> };
>>
>> +&sdmmc_clk {
>> + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
>> +};
>> +
>> &uart0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0m0_xfer>;
>>
>>
>> Changing clk drive strength seem to be something that has been done in
>> Radxa vendor kernel [1], could be something that we can include if it
>> fixes your issue.
>
> This seems to improve the situation a little, but doesn't solve the
> issue. Among more than ten times of testing, the tuning process only
> worked twice.
>
>> The kernel I tested was built from [2].
>
> I've tried this branch as well, but things don't improve.
>
> Do you consider lower the clock-frequency acceptable?
Sure, I will include the max-frequency = <100000000> in a v2 shortly.
Regards,
Jonas
>
>> [1] https://github.com/radxa/kernel/commit/e9b33cbc97a902560d3f3b43b4d36a1a0ac68a50
>> [2] https://github.com/Kwiboo/linux-rockchip/commits/next-20250708-rk3528-boards/
>>
>> Regards,
>> Jonas
>>
>>>
>>> Regards,
>>> Yao Zi
>>
>
> Regards,
> Yao Zi
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