From: Thierry Reding <treding@nvidia.com>

Add the stream IDs for various hardware blocks found on Tegra264. These
are allocated as blocks of 256 IDs and each block can be subdivided for
additional fine-grained isolation if needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 include/dt-bindings/memory/nvidia,tegra264.h | 50 ++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h
index d6cb0c9698f2..521405c01f84 100644
--- a/include/dt-bindings/memory/nvidia,tegra264.h
+++ b/include/dt-bindings/memory/nvidia,tegra264.h
@@ -4,6 +4,56 @@
 #ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
 #define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
 
+#define TEGRA264_SID(x) ((x) << 8)
+
+/*
+ * SMMU stream IDs
+ */
+
+#define TEGRA264_SID_AON       TEGRA264_SID(0x01)
+#define TEGRA264_SID_APE       TEGRA264_SID(0x02)
+#define TEGRA264_SID_ETR       TEGRA264_SID(0x03)
+#define TEGRA264_SID_BPMP      TEGRA264_SID(0x04)
+#define TEGRA264_SID_DCE       TEGRA264_SID(0x05)
+#define TEGRA264_SID_EQOS      TEGRA264_SID(0x06)
+#define TEGRA264_SID_GPCDMA    TEGRA264_SID(0x08)
+#define TEGRA264_SID_DISP      TEGRA264_SID(0x09)
+#define TEGRA264_SID_HDA       TEGRA264_SID(0x0a)
+#define TEGRA264_SID_HOST1X    TEGRA264_SID(0x0b)
+#define TEGRA264_SID_ISP0      TEGRA264_SID(0x0c)
+#define TEGRA264_SID_ISP1      TEGRA264_SID(0x0d)
+#define TEGRA264_SID_PMA0      TEGRA264_SID(0x0e)
+#define TEGRA264_SID_FSI0      TEGRA264_SID(0x0f)
+#define TEGRA264_SID_FSI1      TEGRA264_SID(0x10)
+#define TEGRA264_SID_PVA       TEGRA264_SID(0x11)
+#define TEGRA264_SID_SDMMC0    TEGRA264_SID(0x12)
+#define TEGRA264_SID_MGBE0     TEGRA264_SID(0x13)
+#define TEGRA264_SID_MGBE1     TEGRA264_SID(0x14)
+#define TEGRA264_SID_MGBE2     TEGRA264_SID(0x15)
+#define TEGRA264_SID_MGBE3     TEGRA264_SID(0x16)
+#define TEGRA264_SID_MSSSEQ    TEGRA264_SID(0x17)
+#define TEGRA264_SID_SE        TEGRA264_SID(0x18)
+#define TEGRA264_SID_SEU1      TEGRA264_SID(0x19)
+#define TEGRA264_SID_SEU2      TEGRA264_SID(0x1a)
+#define TEGRA264_SID_SEU3      TEGRA264_SID(0x1b)
+#define TEGRA264_SID_PSC       TEGRA264_SID(0x1c)
+#define TEGRA264_SID_OESP      TEGRA264_SID(0x23)
+#define TEGRA264_SID_SB        TEGRA264_SID(0x24)
+#define TEGRA264_SID_XSPI0     TEGRA264_SID(0x25)
+#define TEGRA264_SID_TSEC      TEGRA264_SID(0x29)
+#define TEGRA264_SID_UFS       TEGRA264_SID(0x2a)
+#define TEGRA264_SID_RCE       TEGRA264_SID(0x2b)
+#define TEGRA264_SID_RCE1      TEGRA264_SID(0x2c)
+#define TEGRA264_SID_VI        TEGRA264_SID(0x2e)
+#define TEGRA264_SID_VI1       TEGRA264_SID(0x2f)
+#define TEGRA264_SID_VIC       TEGRA264_SID(0x30)
+#define TEGRA264_SID_XUSB_DEV  TEGRA264_SID(0x32)
+#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33)
+#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34)
+#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35)
+#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36)
+#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37)
+
 /*
  * memory client IDs
  */
-- 
2.50.0

On 08/07/2025 12:52, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add the stream IDs for various hardware blocks found on Tegra264. These
> are allocated as blocks of 256 IDs and each block can be subdivided for
> additional fine-grained isolation if needed.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  include/dt-bindings/memory/nvidia,tegra264.h | 50 ++++++++++++++++++++

Please squash it (you can take authorship and add co-developed), but
adding given bindings and bindings header for new device is one patch.
Not three.


Best regards,
Krzysztof

On Wed, Jul 09, 2025 at 08:21:53PM +0200, Krzysztof Kozlowski wrote:
> On 08/07/2025 12:52, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Add the stream IDs for various hardware blocks found on Tegra264. These
> > are allocated as blocks of 256 IDs and each block can be subdivided for
> > additional fine-grained isolation if needed.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  include/dt-bindings/memory/nvidia,tegra264.h | 50 ++++++++++++++++++++
> 
> Please squash it (you can take authorship and add co-developed), but
> adding given bindings and bindings header for new device is one patch.
> Not three.

Will do.

Thanks,
Thierry