From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add SDHI0-SDHI1 nodes to RZ/N2H ("R9A09G087") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
- Added "Reviewed-by" tag for patch 2/4 and 3/4.
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 7452aca6b05b..4da21199d22e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ sdhi0: mmc@92080000 {
+ compatible = "renesas,sdhi-r9a09g087",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92080000 0 0x10000>;
+ interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1212>,
+ <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi0_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI0-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
+
+ sdhi1: mmc@92090000 {
+ compatible = "renesas,sdhi-r9a09g087",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92090000 0 0x10000>;
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1213>,
+ <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
};
timer {
--
2.49.0