[PATCH v4 0/2] Fix PLL lock timeout and calibration wait time

Devarsh Thakkar posted 2 patches 3 months ago
drivers/phy/cadence/cdns-dphy.c | 126 ++++++++++++++++++++++++--------
1 file changed, 94 insertions(+), 32 deletions(-)
[PATCH v4 0/2] Fix PLL lock timeout and calibration wait time
Posted by Devarsh Thakkar 3 months ago
This fixes PLL lockup and O_CMN_READY timeout by moving the polling
function after common state machine gets enabled. Also fix the
calibration wait time to optimize the polling time.

NOTE: This needs to be applied on top of  
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/           
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/           
  from the series:                                                                                  
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/    

Changelog:
V4:                                                                                                 
- Optimize wait_for_pll_lock, wait_for_cmn_ready calls to oneline                                   
  using conditional operator                                                                        
- Remove superflous init for ret variable in cdns_dphy_configure                                    
- Enable pll and psm ref clocks before configuring PLL                                              
- Update commit message to refer to TRM                                                             
- Rebased on top of:                                                                                
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/           
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/           
  from the series:                                                                                  
  https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/    

V3: 
-   Use read-modify-write for using calibrated value for PLL
    lock time
-   Move out PLL clock configuration part to power_on function

V2: Separate patch for calibration logic and
    return error code on polling 

Previous versions:
V3: https://lore.kernel.org/all/20250502033451.2291330-1-devarsht@ti.com/
V2: https://lore.kernel.org/all/20250326152320.3835249-1-devarsht@ti.com/
V1: https://lore.kernel.org/all/20241230125319.941372-1-devarsht@ti.com/

Test logs:
Link: https://gist.github.com/devarsht/d08d851399ca327e5594266a8d66d478

Rangediff:
V3->V4:
https://gist.github.com/devarsht/e4db52e1f4aec2d45596b3ed019e92ef

V2->V3:
https://gist.github.com/devarsht/c4d2c4f6715ec7aa4df4cb2c7991b7aa

Devarsh Thakkar (2):
  phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
  phy: cadence: cdns-dphy: Update calibration wait time for startup
    state machine

 drivers/phy/cadence/cdns-dphy.c | 126 ++++++++++++++++++++++++--------
 1 file changed, 94 insertions(+), 32 deletions(-)

-- 
2.39.1
Re: [PATCH v4 0/2] Fix PLL lock timeout and calibration wait time
Posted by Vinod Koul 3 weeks, 6 days ago
On Fri, 04 Jul 2025 18:29:13 +0530, Devarsh Thakkar wrote:
> This fixes PLL lockup and O_CMN_READY timeout by moving the polling
> function after common state machine gets enabled. Also fix the
> calibration wait time to optimize the polling time.
> 
> NOTE: This needs to be applied on top of
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/
>   from the series:
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/
> 
> [...]

Applied, thanks!

[1/2] phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
      commit: 284fb19a3ffb1083c3ad9c00d29749d09dddb99c
[2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine
      commit: 2c27aaee934a1b5229152fe33a14f1fdf50da143

Best regards,
-- 
~Vinod
Re: [PATCH v4 0/2] Fix PLL lock timeout and calibration wait time
Posted by Tomi Valkeinen 2 months, 2 weeks ago
Hi,

On 04/07/2025 15:59, Devarsh Thakkar wrote:
> This fixes PLL lockup and O_CMN_READY timeout by moving the polling
> function after common state machine gets enabled. Also fix the
> calibration wait time to optimize the polling time.
> 
> NOTE: This needs to be applied on top of  
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/           
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/           
>   from the series:                                                                                  
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/    
> 
> Changelog:
> V4:                                                                                                 
> - Optimize wait_for_pll_lock, wait_for_cmn_ready calls to oneline                                   
>   using conditional operator                                                                        
> - Remove superflous init for ret variable in cdns_dphy_configure                                    
> - Enable pll and psm ref clocks before configuring PLL                                              
> - Update commit message to refer to TRM                                                             
> - Rebased on top of:                                                                                
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/           
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/           
>   from the series:                                                                                  
>   https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/    
> 
> V3: 
> -   Use read-modify-write for using calibrated value for PLL
>     lock time
> -   Move out PLL clock configuration part to power_on function
> 
> V2: Separate patch for calibration logic and
>     return error code on polling 
> 
> Previous versions:
> V3: https://lore.kernel.org/all/20250502033451.2291330-1-devarsht@ti.com/
> V2: https://lore.kernel.org/all/20250326152320.3835249-1-devarsht@ti.com/
> V1: https://lore.kernel.org/all/20241230125319.941372-1-devarsht@ti.com/
> 
> Test logs:
> Link: https://gist.github.com/devarsht/d08d851399ca327e5594266a8d66d478
> 
> Rangediff:
> V3->V4:
> https://gist.github.com/devarsht/e4db52e1f4aec2d45596b3ed019e92ef
> 
> V2->V3:
> https://gist.github.com/devarsht/c4d2c4f6715ec7aa4df4cb2c7991b7aa
> 
> Devarsh Thakkar (2):
>   phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
>   phy: cadence: cdns-dphy: Update calibration wait time for startup
>     state machine
> 
>  drivers/phy/cadence/cdns-dphy.c | 126 ++++++++++++++++++++++++--------
>  1 file changed, 94 insertions(+), 32 deletions(-)
> 

For the series:

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

 Tomi