.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 138 ++++++++++++++++++ 3 files changed, 181 insertions(+), 1 deletion(-)
This series adds document, phy, configs support for PCIe in QCS615.
This series depend on the dt-bindings change
https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
---
Have following changes:
- Add a new Document the QCS615 PCIe Controller
- Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence.
- Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc.
Changes in v8:
- Fix scripts/checkpatch.pl error (Krzystof)
- Link to v7: https://lore.kernel.org/all/20250702103549.712039-1-ziyue.zhang@oss.qualcomm.com/
Changes in v7:
- Add Fixes tag to phy bindings patch (Johan)
- QCS615 is Gen3 controller but Gen2 phy, so limited max link speed to Gen2.
- Remove eq-presets-8gts and oppopp-8000000 for only support Gen2.
- Link to v6: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/
Changes in v6:
- Change PCIe equalization setting to one lane
- Add reviewed by tags
- Link to v5: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/
Changes in v5:
- Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded
version of sm8150, which can share the same yaml.
- Drop compatible enrty in driver and use sm8150's enrty (Krzysztof)
- Fix the DT format problem (Konrad)
- Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/
Changes in v4:
- Fixed compile error found by kernel test robot(Krzysztof)
- Update DT format (Konrad & Krzysztof)
- Remove QCS8550 compatible use QCS615 compatible only (Konrad)
- Update phy dt bindings to fix the dtb check errors.
- Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/
Changes in v3:
- Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry)
- Removed the driver patch and using fallback method (Mani)
- Update DT format, keep it same with the x1e801000.dtsi (Konrad)
- Update DT commit message (Bojor)
- Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/
Changes in v2:
- Update commit message for qcs615 phy
- Update qcs615 phy, using lowercase hex
- Removed redundant function
- split the soc dtsi and the platform dts into two changes
- Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/
Krishna chaitanya chundru (2):
arm64: dts: qcom: qcs615: enable pcie
arm64: dts: qcom: qcs615-ride: Enable PCIe interface
Ziyue Zhang (1):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
for QCS615
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +-
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++
arch/arm64/boot/dts/qcom/qcs615.dtsi | 138 ++++++++++++++++++
3 files changed, 181 insertions(+), 1 deletion(-)
base-commit: 3f804361f3b9af33e00b90ec9cb5afcc96831e60
--
2.34.1
On 7/3/2025 5:56 PM, Ziyue Zhang wrote: > This series adds document, phy, configs support for PCIe in QCS615. > > This series depend on the dt-bindings change > https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/ > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> > --- > Have following changes: > - Add a new Document the QCS615 PCIe Controller > - Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence. > - Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc. > > Changes in v8: > - Fix scripts/checkpatch.pl error (Krzystof) > - Link to v7: https://lore.kernel.org/all/20250702103549.712039-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v7: > - Add Fixes tag to phy bindings patch (Johan) > - QCS615 is Gen3 controller but Gen2 phy, so limited max link speed to Gen2. > - Remove eq-presets-8gts and oppopp-8000000 for only support Gen2. > - Link to v6: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/ > > Changes in v6: > - Change PCIe equalization setting to one lane > - Add reviewed by tags > - Link to v5: https://lore.kernel.org/all/t6bwkld55a2dcozxz7rxnvdgpjis6oveqzkh4s7nvxgikws4rl@fn2sd7zlabhe/ > > Changes in v5: > - Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded > version of sm8150, which can share the same yaml. > - Drop compatible enrty in driver and use sm8150's enrty (Krzysztof) > - Fix the DT format problem (Konrad) > - Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/ > > Changes in v4: > - Fixed compile error found by kernel test robot(Krzysztof) > - Update DT format (Konrad & Krzysztof) > - Remove QCS8550 compatible use QCS615 compatible only (Konrad) > - Update phy dt bindings to fix the dtb check errors. > - Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/ > > Changes in v3: > - Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry) > - Removed the driver patch and using fallback method (Mani) > - Update DT format, keep it same with the x1e801000.dtsi (Konrad) > - Update DT commit message (Bojor) > - Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/ > > Changes in v2: > - Update commit message for qcs615 phy > - Update qcs615 phy, using lowercase hex > - Removed redundant function > - split the soc dtsi and the platform dts into two changes > - Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/ > > > Krishna chaitanya chundru (2): > arm64: dts: qcom: qcs615: enable pcie > arm64: dts: qcom: qcs615-ride: Enable PCIe interface > > Ziyue Zhang (1): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings > for QCS615 > > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +- > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++ > arch/arm64/boot/dts/qcom/qcs615.dtsi | 138 ++++++++++++++++++ > 3 files changed, 181 insertions(+), 1 deletion(-) > > > base-commit: 3f804361f3b9af33e00b90ec9cb5afcc96831e60 Hi Maintainers, It seems the patches get reviewed tag for a long time, can you give this series further comment or help me to merge them ? Thanks very much. BRs Ziyue
On Thu, 03 Jul 2025 02:56:27 -0700, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS615.
>
> This series depend on the dt-bindings change
> https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/
>
>
Applied, thanks!
[1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
commit: dfef90f29811b5b8bc6353e259cac6134a88671f
Best regards,
--
~Vinod
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