On Thu, Jul 03, 2025 at 11:40:24AM +0800, Peng Fan wrote:
> Add nodes for LVDS/DISPLAY CSR.
>
> Add clock-ldb-pll-div7 node which is used for clock source of DISPLAY CSR.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 45b8da758e87771c0775eb799ce2da3aac37c060..657c81b6016f21270a1b13d636af72c14ab4f8ef 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -3,6 +3,8 @@
> * Copyright 2025 NXP
> */
>
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
> +
> #include "imx94.dtsi"
>
> / {
> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
> cache-unified;
> };
> };
> +
> + clock-ldb-pll-div7 {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> + clock-div = <7>;
> + clock-mult = <1>;
> + clock-output-names = "ldb_pll_div7";
> + };
> +
> + soc {
> + dispmix_csr: syscon@4b010000 {
> + compatible = "nxp,imx94-display-csr", "syscon";
> + reg = <0x0 0x4b010000 0x0 0x10000>;
> + clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> + #clock-cells = <1>;
> + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> + assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
> + <&scmi_clk IMX94_CLK_DISPAPB>;
> + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
> + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
> + assigned-clock-rates = <400000000>, <133333333>;
> + };
> +
> + lvds_csr: syscon@4b0c0000 {
> + compatible = "nxp,imx94-lvds-csr", "syscon";
> + reg = <0x0 0x4b0c0000 0x0 0x10000>;
> + clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> + #clock-cells = <1>;
> + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> + };
> + };
> };
>
> --
> 2.37.1
>