The hardware EVT version for exynosautov920 has been updated, with EVT2
confirmed as the final production version. Accordingly, this patch updates
the UFS PHY calibration settings to match EVT2 hardware characteristics.

This ensures stable operation and optimal performance on the finalized EVT2
hardware revision.

Tested on exynosautov920 EVT2.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 drivers/phy/samsung/phy-exynosautov920-ufs.c | 39 +++++++-------------
 drivers/phy/samsung/phy-samsung-ufs.h        |  1 -
 2 files changed, 14 insertions(+), 26 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c b/drivers/phy/samsung/phy-exynosautov920-ufs.c
index 21ef79c42f95..5ff9fc3a0615 100644
--- a/drivers/phy/samsung/phy-exynosautov920-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c
@@ -12,8 +12,7 @@
 #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
 #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 
-#define EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xce4
-
+#define EXYNOSAUTOV920_CAL_DONE_OFFSET				0xce0
 #define PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
 #define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
@@ -32,7 +31,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0a, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
-	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x11, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0c, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2e1, 0xc0, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x22d, 0xf8, PWR_MODE_ANY),
@@ -46,6 +45,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x23e, 0x14, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x23f, 0x13, PWR_MODE_ANY),
 
+	PHY_TRSV_REG_CFG_AUTOV920(0x36e, 0x05, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4a, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
@@ -76,6 +76,10 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x2bc, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2bd, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2be, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2e4, 0x1a, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2ed, 0x25, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x269, 0x1a, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2f4, 0x2f, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34b, 0x01, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34c, 0x24, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34d, 0x23, PWR_MODE_ANY),
@@ -107,40 +111,25 @@ static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
 
 #define DELAY_IN_US	40
 #define RETRY_CNT	100
-#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8
+#define EXYNOSAUTOV920_CAL_DONE_MASK	0x8
 
-int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
+static int exynosautov920_ufs_phy_wait_for_cal(struct phy *phy, u8 lane)
 {
 	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
 	u32 reg, i;
 
-	struct samsung_ufs_phy_cfg cfg[4] = {
-		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
-		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
-		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
-		END_UFS_PHY_CFG,
-	};
-
 	for (i = 0; i < RETRY_CNT; i++) {
 		udelay(DELAY_IN_US);
 
-		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
+		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CAL_DONE_OFFSET +
 			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
 
-		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
-					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
-			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
+		if ((reg & EXYNOSAUTOV920_CAL_DONE_MASK)
+					== EXYNOSAUTOV920_CAL_DONE_MASK)
 			return 0;
-		}
-
-		udelay(DELAY_IN_US);
-
-		/* Disable and enable CDR */
-		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
-		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
 	}
 
-	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
+	dev_err(ufs_phy->dev, "failed to wait for cal done\n");
 	return -ETIMEDOUT;
 }
 
@@ -164,5 +153,5 @@ const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
 	.clk_list = exynosautov920_ufs_phy_clks,
 	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
 	.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
-	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
+	.wait_for_cal = exynosautov920_ufs_phy_wait_for_cal,
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index a28f148081d1..895741e800da 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -143,7 +143,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
 }
 
 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
-int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
 void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
 			    const struct samsung_ufs_phy_cfg *cfg, u8 lane);
 
-- 
2.45.2

Hi Sowon, 

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Wednesday, July 2, 2025 7:03 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH 1/5] phy: samsung-ufs: update calibration settings for EVT2
> 
> The hardware EVT version for exynosautov920 has been updated, with EVT2
> confirmed as the final production version. Accordingly, this patch updates the
> UFS PHY calibration settings to match EVT2 hardware characteristics.
> 
This patch does more then what is mentioned here, 
please update the commit with all the changes so that we understand why the changes was done. 
.
.
.[snip]
> -#define EXYNOSAUTOV920_CDR_LOCK_OFFSET
> 	0xce4
> -
> +#define EXYNOSAUTOV920_CAL_DONE_OFFSET
> 	0xce0
Any reason for not using CRD lock and using Cal Done?