1. Patchew
  2. linux
  3. [PATCH v4 0/4] Add support for GBETH IPs found on RZ/G3E SoCs
  4. View patch

[PATCH v4 3/4] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC

John Madieu posted 4 patches 7 months, 1 week ago
[PATCH v4 3/4] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC
Posted by John Madieu 7 months, 1 week ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support to configure the PFC_OEN register on the RZ/G3E SoC for
specific pins that require direction control via output-enable.

On the RZ/G3E SoC, certain pins such as TXC_TXCLK must be switchable
between input and output modes depending on the PHY interface mode
(MII or RGMII). This behavior maps to the `output-enable` property in
the device tree and requires configuring the PFC_OEN register.

Update the r9a09g047_variable_pin_cfg array to include PB1, PE1, PL0,
PL1, PL2, and PL4 with PIN_CFG_OEN flags to indicate support for this
feature. Define a new rzg3e_hwcfg structure with SoC-specific pin names
used for OEN bit mapping.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---

Changes:

v4: new patch

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 45 ++++++++++++++++++++++---
 1 file changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 792ca70bd9d1..00847a743d1f 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -398,6 +398,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
@@ -406,6 +414,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
@@ -425,6 +441,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS),
 };
 
 static const u64 r9a09g057_variable_pin_cfg[] = {
@@ -2052,17 +2076,17 @@ static const u64 r9a09g047_gpio_configs[] = {
 	RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS),	/* P8 */
 	0x0,
 	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a),			/* PA */
-	RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS),	/* PB */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b),			/* PB */
 	RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS),	/* PC */
 	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d),			/* PD */
-	RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS),	/* PE */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e),			/* PE */
 	RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS),	/* PF */
 	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30),			/* PG */
 	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31),			/* PH */
 	0x0,
 	RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33),			/* PJ */
 	RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS),	/* PK */
-	RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS),	/* PL */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35),			/* PL */
 	RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS),	/* PM */
 	0x0,
 	0x0,
@@ -3283,6 +3307,19 @@ static const char * const rzv2h_oen_pin_names[] = {
 	"XSPI0_CKN", "XSPI0_CKP"
 };
 
+static const char * const rzg3e_oen_pin_names[] = {
+	"PB1", "PE1", "PL4", "PL1", "PL2", "PL0"
+};
+
+static const struct rzg2l_hwcfg rzg3e_hwcfg = {
+	.regs = {
+		.pwpr = 0x3c04,
+	},
+	.tint_start_index = 17,
+	.oen_pin_names = rzg3e_oen_pin_names,
+	.oen_pin_names_len = ARRAY_SIZE(rzg3e_oen_pin_names),
+};
+
 static const struct rzg2l_hwcfg rzv2h_hwcfg = {
 	.regs = {
 		.pwpr = 0x3c04,
@@ -3352,7 +3389,7 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
 	.dedicated_pins = rzg3e_dedicated_pins,
 	.n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
 	.n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
-	.hwcfg = &rzv2h_hwcfg,
+	.hwcfg = &rzg3e_hwcfg,
 	.variable_pin_cfg = r9a09g047_variable_pin_cfg,
 	.n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
 	.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
-- 
2.25.1
Re: [PATCH v4 3/4] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC
Posted by Geert Uytterhoeven 7 months, 1 week ago 
Hi John, Prabhakar,

On Wed, 2 Jul 2025 at 02:57, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support to configure the PFC_OEN register on the RZ/G3E SoC for
> specific pins that require direction control via output-enable.
>
> On the RZ/G3E SoC, certain pins such as TXC_TXCLK must be switchable
> between input and output modes depending on the PHY interface mode
> (MII or RGMII). This behavior maps to the `output-enable` property in
> the device tree and requires configuring the PFC_OEN register.
>
> Update the r9a09g047_variable_pin_cfg array to include PB1, PE1, PL0,
> PL1, PL2, and PL4 with PIN_CFG_OEN flags to indicate support for this
> feature. Define a new rzg3e_hwcfg structure with SoC-specific pin names
> used for OEN bit mapping.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c

> @@ -3283,6 +3307,19 @@ static const char * const rzv2h_oen_pin_names[] = {
>         "XSPI0_CKN", "XSPI0_CKP"
>  };
>
> +static const char * const rzg3e_oen_pin_names[] = {
> +       "PB1", "PE1", "PL4", "PL1", "PL2", "PL0"
> +};
> +
> +static const struct rzg2l_hwcfg rzg3e_hwcfg = {
> +       .regs = {
> +               .pwpr = 0x3c04,
> +       },
> +       .tint_start_index = 17,
> +       .oen_pin_names = rzg3e_oen_pin_names,
> +       .oen_pin_names_len = ARRAY_SIZE(rzg3e_oen_pin_names),
> +};
> +
>  static const struct rzg2l_hwcfg rzv2h_hwcfg = {
>         .regs = {
>                 .pwpr = 0x3c04,
> @@ -3352,7 +3389,7 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
>         .dedicated_pins = rzg3e_dedicated_pins,
>         .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
>         .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
> -       .hwcfg = &rzv2h_hwcfg,
> +       .hwcfg = &rzg3e_hwcfg,
>         .variable_pin_cfg = r9a09g047_variable_pin_cfg,
>         .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
>         .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),

I would rather use the existing .oen_{read,write}() abstraction,
and thus provide new rzg3e_oen_{read,write}() implementations:

    -    .oen_read = &rzv2h_oen_read,
    -    .oen_write = &rzv2h_oen_write,
    +    .oen_read = &rzg3e_oen_read,
    +    .oen_write = &rzg3e_oen_write,

Of course this requires refactoring the existing rzv2h_pin_to_oen_bit()
and rzv2h_oen_{read,write}() functions to avoid duplication.
Do you agree?

The actual pin parts LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH v4 3/4] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC
Posted by Lad, Prabhakar 7 months, 1 week ago 
Hi Geert,

Thank you for the review.

On Wed, Jul 2, 2025 at 10:55 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi John, Prabhakar,
>
> On Wed, 2 Jul 2025 at 02:57, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add support to configure the PFC_OEN register on the RZ/G3E SoC for
> > specific pins that require direction control via output-enable.
> >
> > On the RZ/G3E SoC, certain pins such as TXC_TXCLK must be switchable
> > between input and output modes depending on the PHY interface mode
> > (MII or RGMII). This behavior maps to the `output-enable` property in
> > the device tree and requires configuring the PFC_OEN register.
> >
> > Update the r9a09g047_variable_pin_cfg array to include PB1, PE1, PL0,
> > PL1, PL2, and PL4 with PIN_CFG_OEN flags to indicate support for this
> > feature. Define a new rzg3e_hwcfg structure with SoC-specific pin names
> > used for OEN bit mapping.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>
> > @@ -3283,6 +3307,19 @@ static const char * const rzv2h_oen_pin_names[] = {
> >         "XSPI0_CKN", "XSPI0_CKP"
> >  };
> >
> > +static const char * const rzg3e_oen_pin_names[] = {
> > +       "PB1", "PE1", "PL4", "PL1", "PL2", "PL0"
> > +};
> > +
> > +static const struct rzg2l_hwcfg rzg3e_hwcfg = {
> > +       .regs = {
> > +               .pwpr = 0x3c04,
> > +       },
> > +       .tint_start_index = 17,
> > +       .oen_pin_names = rzg3e_oen_pin_names,
> > +       .oen_pin_names_len = ARRAY_SIZE(rzg3e_oen_pin_names),
> > +};
> > +
> >  static const struct rzg2l_hwcfg rzv2h_hwcfg = {
> >         .regs = {
> >                 .pwpr = 0x3c04,
> > @@ -3352,7 +3389,7 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
> >         .dedicated_pins = rzg3e_dedicated_pins,
> >         .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
> >         .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
> > -       .hwcfg = &rzv2h_hwcfg,
> > +       .hwcfg = &rzg3e_hwcfg,
> >         .variable_pin_cfg = r9a09g047_variable_pin_cfg,
> >         .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
> >         .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
>
> I would rather use the existing .oen_{read,write}() abstraction,
> and thus provide new rzg3e_oen_{read,write}() implementations:
>
Ok.

>     -    .oen_read = &rzv2h_oen_read,
>     -    .oen_write = &rzv2h_oen_write,
>     +    .oen_read = &rzg3e_oen_read,
>     +    .oen_write = &rzg3e_oen_write,
>
> Of course this requires refactoring the existing rzv2h_pin_to_oen_bit()
> and rzv2h_oen_{read,write}() functions to avoid duplication.
> Do you agree?
>
Agreed.

Cheers,
Prabhakar

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.