IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644
--- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml
+++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
@@ -18,6 +18,12 @@ properties:
items:
- enum:
- qcom,apq8064-imem
+ - qcom,ipq8074-imem
+ - qcom,ipq6018-imem
+ - qcom,ipq5018-imem
+ - qcom,ipq9574-imem
+ - qcom,ipq5332-imem
+ - qcom,ipq5424-imem
- qcom,msm8226-imem
- qcom,msm8974-imem
- qcom,msm8976-imem
--
2.34.1
On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: > IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. > > Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> > --- > Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Where is the changelog? This is not a v1. > diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml > index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 > --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml > +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml > @@ -18,6 +18,12 @@ properties: > items: > - enum: > - qcom,apq8064-imem > + - qcom,ipq8074-imem > + - qcom,ipq6018-imem > + - qcom,ipq5018-imem > + - qcom,ipq9574-imem > + - qcom,ipq5332-imem > + - qcom,ipq5424-imem Random order, no, follow existing style. This applies for every qcom binding and you received such feedbacks in the past. Best regards, Krzysztof
On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: > On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. >> >> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> >> --- >> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) > > Where is the changelog? This is not a v1. This is the v1. The series[1] I pointed out describes only for the IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the appropriate numbering. [1] https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ > >> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 >> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >> @@ -18,6 +18,12 @@ properties: >> items: >> - enum: >> - qcom,apq8064-imem >> + - qcom,ipq8074-imem >> + - qcom,ipq6018-imem >> + - qcom,ipq5018-imem >> + - qcom,ipq9574-imem >> + - qcom,ipq5332-imem >> + - qcom,ipq5424-imem > Random order, no, follow existing style. This applies for every qcom > binding and you received such feedbacks in the past. Apologies — I arranged them based on the evolutionary order of SoCs. I’ll correct this in v2 and ensure it’s handled properly in the future. > > Best regards, > Krzysztof
On 02/07/2025 12:46, Kathiravan Thirumoorthy wrote: > > On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: >> On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >>> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. >>> >>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> >>> --- >>> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >>> 1 file changed, 6 insertions(+) >> >> Where is the changelog? This is not a v1. > > This is the v1. The series[1] I pointed out describes only for the > IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the > appropriate numbering. > > [1] > https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ But IPQ5424 is already there, so you reworked that patch. > >> >>> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>> index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 >>> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>> @@ -18,6 +18,12 @@ properties: >>> items: >>> - enum: >>> - qcom,apq8064-imem >>> + - qcom,ipq8074-imem >>> + - qcom,ipq6018-imem >>> + - qcom,ipq5018-imem >>> + - qcom,ipq9574-imem >>> + - qcom,ipq5332-imem >>> + - qcom,ipq5424-imem >> Random order, no, follow existing style. This applies for every qcom >> binding and you received such feedbacks in the past. > > Apologies — I arranged them based on the evolutionary order of SoCs. Where is such ordering documented? How is it expressed in your internal guideline for example? Best regards, Krzysztof
On 7/2/2025 4:18 PM, Krzysztof Kozlowski wrote: > On 02/07/2025 12:46, Kathiravan Thirumoorthy wrote: >> On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: >>> On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >>>> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. >>>> >>>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> >>>> --- >>>> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>> Where is the changelog? This is not a v1. >> This is the v1. The series[1] I pointed out describes only for the >> IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the >> appropriate numbering. >> >> [1] >> https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ > But IPQ5424 is already there, so you reworked that patch. Okay, so this should be V6? > > >>>> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 >>>> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> @@ -18,6 +18,12 @@ properties: >>>> items: >>>> - enum: >>>> - qcom,apq8064-imem >>>> + - qcom,ipq8074-imem >>>> + - qcom,ipq6018-imem >>>> + - qcom,ipq5018-imem >>>> + - qcom,ipq9574-imem >>>> + - qcom,ipq5332-imem >>>> + - qcom,ipq5424-imem >>> Random order, no, follow existing style. This applies for every qcom >>> binding and you received such feedbacks in the past. >> Apologies — I arranged them based on the evolutionary order of SoCs. > Where is such ordering documented? How is it expressed in your internal > guideline for example? I made the mistake unintentionally and apologized for the same! > > Best regards, > Krzysztof
On 7/2/2025 4:29 PM, Kathiravan Thirumoorthy wrote: > > On 7/2/2025 4:18 PM, Krzysztof Kozlowski wrote: >> On 02/07/2025 12:46, Kathiravan Thirumoorthy wrote: >>> On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: >>>> On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >>>>> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the >>>>> same. >>>>> >>>>> Signed-off-by: Kathiravan Thirumoorthy >>>>> <kathiravan.thirumoorthy@oss.qualcomm.com> >>>>> --- >>>>> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >>>>> 1 file changed, 6 insertions(+) >>>> Where is the changelog? This is not a v1. >>> This is the v1. The series[1] I pointed out describes only for the >>> IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the >>> appropriate numbering. >>> >>> [1] >>> https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ >>> >> But IPQ5424 is already there, so you reworked that patch. > Okay, so this should be V6? Let me drop the IPQ5424 support and send the V2. I hope that is fine. >> >> >>>>> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> index >>>>> 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda >>>>> 100644 >>>>> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>>> @@ -18,6 +18,12 @@ properties: >>>>> items: >>>>> - enum: >>>>> - qcom,apq8064-imem >>>>> + - qcom,ipq8074-imem >>>>> + - qcom,ipq6018-imem >>>>> + - qcom,ipq5018-imem >>>>> + - qcom,ipq9574-imem >>>>> + - qcom,ipq5332-imem >>>>> + - qcom,ipq5424-imem >>>> Random order, no, follow existing style. This applies for every qcom >>>> binding and you received such feedbacks in the past. >>> Apologies — I arranged them based on the evolutionary order of SoCs. >> Where is such ordering documented? How is it expressed in your internal >> guideline for example? > I made the mistake unintentionally and apologized for the same! >> >> Best regards, >> Krzysztof
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