On 2025/6/30 15:32, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
>
> On Mon, Jun 30, 2025 at 12:16:01PM +0800, hans.zhang@cixtech.com wrote:
>> From: Hans Zhang <hans.zhang@cixtech.com>
>>
>> Add PCIe RC support on Orion O6 board.
>>
>> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
>> Reviewed-by: Peter Chen <peter.chen@cixtech.com>
>> Reviewed-by: Manikandan K Pillai <mpillai@cadence.com>
>
> Where? Please provide lore links. The happened AFTER the SoB, so they
> must have been made public, right?
>
Dear Krzysztof,
I have replied to patch 12/14. The subsequent versions will be deleted.
>> ---
>> arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>> index d74964d53c3b..44710d54ddad 100644
>> --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>> +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>> @@ -37,3 +37,23 @@ linux,cma {
>> &uart2 {
>> status = "okay";
>> };
>> +
>> +&pcie_x8_rc {
>> + status = "okay";
>
> And really two people reviewed this trivial changes? Really?
>
> Plus what their review actually checked? This is obviously wrong - not
> following DTS coding style, so what such review meant? What did it
>
Will delete.
Best regards,
Hans
> Best regards,
> Krzysztof
>