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[PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node

Luo Jie posted 8 patches 3 months, 1 week ago
There is a newer version of this series
[PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node
Posted by Luo Jie 3 months, 1 week ago 
NSS clock controller provides the clocks and resets to the networking
hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
UNIPHY (PCS) blocks.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 2eea8a078595..eb4aa778269c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -730,6 +730,36 @@ frame@f42d000 {
 			};
 		};
 
+		clock-controller@39b00000 {
+			compatible = "qcom,ipq5424-nsscc";
+			reg = <0 0x39b00000 0 0x800>;
+			clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>,
+				 <&cmn_pll IPQ5424_NSS_300MHZ_CLK>,
+				 <&cmn_pll IPQ5424_PPE_375MHZ_CLK>,
+				 <&gcc GPLL0_OUT_AUX>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <&gcc GCC_NSSCC_CLK>;
+			clock-names = "xo",
+				      "nss",
+				      "ppe",
+				      "gpll0_out",
+				      "uniphy0_rx",
+				      "uniphy0_tx",
+				      "uniphy1_rx",
+				      "uniphy1_tx",
+				      "uniphy2_rx",
+				      "uniphy2_tx",
+				      "bus";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#interconnect-cells = <1>;
+		};
+
 		pcie3: pcie@40000000 {
 			compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
 			reg = <0x0 0x40000000 0x0 0xf1c>,

-- 
2.34.1
Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node
Posted by Konrad Dybcio 3 months, 1 week ago 
On 6/27/25 2:09 PM, Luo Jie wrote:
> NSS clock controller provides the clocks and resets to the networking
> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
> UNIPHY (PCS) blocks.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 2eea8a078595..eb4aa778269c 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -730,6 +730,36 @@ frame@f42d000 {
>  			};
>  		};
>  
> +		clock-controller@39b00000 {
> +			compatible = "qcom,ipq5424-nsscc";
> +			reg = <0 0x39b00000 0 0x800>;

size = 0x100_000

with that:

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad
Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node
Posted by Luo Jie 3 months, 1 week ago 

On 6/28/2025 12:27 AM, Konrad Dybcio wrote:
> On 6/27/25 2:09 PM, Luo Jie wrote:
>> NSS clock controller provides the clocks and resets to the networking
>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
>> UNIPHY (PCS) blocks.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 2eea8a078595..eb4aa778269c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -730,6 +730,36 @@ frame@f42d000 {
>>   			};
>>   		};
>>   
>> +		clock-controller@39b00000 {
>> +			compatible = "qcom,ipq5424-nsscc";
>> +			reg = <0 0x39b00000 0 0x800>;
> 
> size = 0x100_000
> 
> with that:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad

I initially thought that a block size of 0x800 would be sufficient, as
it covers the maximum address range needed for the clock configurations.
However, the NSS clock controller block actually occupies an address
range of 0x80000. I will update this to 0x80000 in the next version.
Thank you for your feedback.
Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node
Posted by Konrad Dybcio 3 months, 1 week ago 

On 01-Jul-25 14:08, Luo Jie wrote:
> 
> 
> On 6/28/2025 12:27 AM, Konrad Dybcio wrote:
>> On 6/27/25 2:09 PM, Luo Jie wrote:
>>> NSS clock controller provides the clocks and resets to the networking
>>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
>>> UNIPHY (PCS) blocks.
>>>
>>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
>>>   1 file changed, 30 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> index 2eea8a078595..eb4aa778269c 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> @@ -730,6 +730,36 @@ frame@f42d000 {
>>>               };
>>>           };
>>>   +        clock-controller@39b00000 {
>>> +            compatible = "qcom,ipq5424-nsscc";
>>> +            reg = <0 0x39b00000 0 0x800>;
>>
>> size = 0x100_000
>>
>> with that:
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Konrad
> 
> I initially thought that a block size of 0x800 would be sufficient, as
> it covers the maximum address range needed for the clock configurations.
> However, the NSS clock controller block actually occupies an address
> range of 0x80000. I will update this to 0x80000 in the next version.
> Thank you for your feedback.

0x80_000 excludes the wrapper region. Please mark it as the entire
0x100_000 that it occupies, no matter if there's anything in there

Konrad
Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node
Posted by Luo Jie 3 months, 1 week ago 

On 7/1/2025 8:10 PM, Konrad Dybcio wrote:
> 
> 
> On 01-Jul-25 14:08, Luo Jie wrote:
>>
>>
>> On 6/28/2025 12:27 AM, Konrad Dybcio wrote:
>>> On 6/27/25 2:09 PM, Luo Jie wrote:
>>>> NSS clock controller provides the clocks and resets to the networking
>>>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
>>>> UNIPHY (PCS) blocks.
>>>>
>>>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++
>>>>    1 file changed, 30 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> index 2eea8a078595..eb4aa778269c 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> @@ -730,6 +730,36 @@ frame@f42d000 {
>>>>                };
>>>>            };
>>>>    +        clock-controller@39b00000 {
>>>> +            compatible = "qcom,ipq5424-nsscc";
>>>> +            reg = <0 0x39b00000 0 0x800>;
>>>
>>> size = 0x100_000
>>>
>>> with that:
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> Konrad
>>
>> I initially thought that a block size of 0x800 would be sufficient, as
>> it covers the maximum address range needed for the clock configurations.
>> However, the NSS clock controller block actually occupies an address
>> range of 0x80000. I will update this to 0x80000 in the next version.
>> Thank you for your feedback.
> 
> 0x80_000 excludes the wrapper region. Please mark it as the entire
> 0x100_000 that it occupies, no matter if there's anything in there
> 
> Konrad

I will update the register region to use the full 0x100_000 range to
cover the entire area, including the wrapper region, as suggested,
thanks.

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