From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index eec6fec19944..2949790e39a9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ sdhi0: mmc@92080000 {
+ compatible = "renesas,sdhi-r9a09g077",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92080000 0 0x10000>;
+ interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1212>,
+ <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi0_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI0-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
+
+ sdhi1: mmc@92090000 {
+ compatible = "renesas,sdhi-r9a09g077",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92090000 0 0x10000>;
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1213>,
+ <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
};
timer {
--
2.49.0
Hi Prabhakar, On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { > interrupt-controller; > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > }; > + > + sdhi0: mmc@92080000 { > + compatible = "renesas,sdhi-r9a09g077", > + "renesas,sdhi-r9a09g057"; > + reg = <0x0 0x92080000 0 0x10000>; > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 1212>, 1112? > + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; > + clock-names = "aclk", "clkh"; > + power-domains = <&cpg>; > + status = "disabled"; > + > + sdhi0_vqmmc: vqmmc-regulator { > + regulator-name = "SDHI0-VQMMC"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + status = "disabled"; > + }; > + }; > + > + sdhi1: mmc@92090000 { > + compatible = "renesas,sdhi-r9a09g077", > + "renesas,sdhi-r9a09g057"; > + reg = <0x0 0x92090000 0 0x10000>; > + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 1213>, 1113? > + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; > + clock-names = "aclk", "clkh"; > + power-domains = <&cpg>; > + status = "disabled"; > + > + sdhi1_vqmmc: vqmmc-regulator { > + regulator-name = "SDHI1-VQMMC"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + status = "disabled"; > + }; > + }; > }; > The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { > > interrupt-controller; > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > > }; > > + > > + sdhi0: mmc@92080000 { > > + compatible = "renesas,sdhi-r9a09g077", > > + "renesas,sdhi-r9a09g057"; > > + reg = <0x0 0x92080000 0 0x10000>; > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD 1212>, > > 1112? > Agreed (and below). Cheers, Prabhakar
Hi Geert, On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Geert, > > Thank you for the review. > > On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > > Hi Prabhakar, > > > > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { > > > interrupt-controller; > > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > > > }; > > > + > > > + sdhi0: mmc@92080000 { > > > + compatible = "renesas,sdhi-r9a09g077", > > > + "renesas,sdhi-r9a09g057"; > > > + reg = <0x0 0x92080000 0 0x10000>; > > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&cpg CPG_MOD 1212>, > > > > 1112? > > > Agreed (and below). > Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register. Cheers, Prabhakar
Hi Prabhakar, On Fri, 4 Jul 2025 at 19:13, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Thanks for your patch! > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > > > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { > > > > interrupt-controller; > > > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > > > > }; > > > > + > > > > + sdhi0: mmc@92080000 { > > > > + compatible = "renesas,sdhi-r9a09g077", > > > > + "renesas,sdhi-r9a09g057"; > > > > + reg = <0x0 0x92080000 0 0x10000>; > > > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&cpg CPG_MOD 1212>, > > > > > > 1112? > > > > > Agreed (and below). > > > Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register. Oops, you're right. Sorry for the noise. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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