From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index f6e5f62b07c4..7ecc4f0b235a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -24,5 +24,6 @@
#define R9A09G077_CLK_PCLKH 12
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
+#define R9A09G077_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index f28166d6015f..925e57703925 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -24,5 +24,6 @@
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
+#define R9A09G087_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
--
2.49.0
Hi Prabhakar, On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as > a core clock for the SDHI IP and operates at 800MHz. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + > include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp. renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and renesas-devel. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Wed, 2 Jul 2025 at 15:37, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas > > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as > > a core clock for the SDHI IP and operates at 800MHz. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + > > include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp. > renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and > renesas-devel. Looks like I can do without the split, as renesas-r9a09g087-dt-binding-defs is based on renesas-r9a09g077-dt-binding-defs. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Wed, Jul 2, 2025 at 7:23 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Wed, 2 Jul 2025 at 15:37, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas > > > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as > > > a core clock for the SDHI IP and operates at 800MHz. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + > > > include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp. > > renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and > > renesas-devel. > > Looks like I can do without the split, as renesas-r9a09g087-dt-binding-defs > is based on renesas-r9a09g077-dt-binding-defs. > Great! I mainly did this to reduce the load on DT maintainers. Cheers, Prabhakar
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