Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
on the SM7635 SoC.
Supported functionality as of this initial submission:
* Debug UART
* Regulators (PM7550, PM8550VS, PMR735B, PM8008)
* Remoteprocs (ADSP, CDSP, MPSS, WPSS)
* Power Button, Volume Keys, Switch
* Display (using simple-framebuffer)
* PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching)
* Camera flash/torch LED
* SD card
* USB
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts | 837 ++++++++++++++++++++++
2 files changed, 838 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 669b888b27a1daa93ac15f47e8b9a302bb0922c2..c06c93a92fb9ce24aed9dee51c0907ab22903ac5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -266,6 +266,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7635-fairphone-fp6.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts
new file mode 100644
index 0000000000000000000000000000000000000000..d687e4e75f21afbe317093cd3b48030354411592
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts
@@ -0,0 +1,837 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+/dts-v1/;
+
+#define PMIV0104_SID 7
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm7635.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmiv0104.dtsi" /* PMIV0108 */
+#include "pmk8550.dtsi" /* PMK7635 */
+#include "pmr735b.dtsi"
+#include "pmxr2230.dtsi" /* PM7550 */
+
+/ {
+ model = "The Fairphone (Gen. 6)";
+ compatible = "fairphone,fp6", "qcom,sm7635";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer0: framebuffer@e3940000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0xe3940000 0x0 (2484 * 1116 * 4)>;
+ width = <1116>;
+ height = <2484>;
+ stride = <(1116 * 4)>;
+ format = "a8r8g8b8";
+ panel = <&panel>;
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pmxr2230_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ switch {
+ label = "Switch";
+ gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_MUTE_DEVICE>;
+ };
+ };
+
+ /* Dummy panel for simple-framebuffer dimension info */
+ panel: panel {
+ compatible = "boe,bj631jhm-t71-d900";
+ width-mm = <65>;
+ height-mm = <146>;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm7635-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+ };
+ };
+ };
+
+ vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ff_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_dvdd: regulator-uw-dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s1b>;
+ };
+
+ vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_avdd0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_ois_vdd: regulator-ois-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "oled_dvdd_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s2b>;
+
+ regulator-boot-on;
+ };
+
+ vreg_s1j: regulator-pm3001a-s1j {
+ compatible = "regulator-fixed";
+ regulator-name = "pm3001a_s1j";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ startup-delay-us = <1000>;
+
+ gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+
+ pinctrl-0 = <&s1j_enable_default>;
+ pinctrl-names = "default";
+ };
+
+ vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtof_ldo_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ /*
+ * ABL is powering down display and controller if this node is
+ * not named exactly "splash_region".
+ */
+ splash_region@e3940000 {
+ reg = <0x0 0xe3940000 0x0 0x2b00000>;
+ no-map;
+ };
+ };
+
+ thermal-zones {
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7550-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1b>;
+ vdd-l2-l3-supply = <&vreg_s3b>;
+ vdd-l4-l5-supply = <&vreg_s2b>;
+ vdd-l6-supply = <&vreg_s2b>;
+ vdd-l7-supply = <&vreg_s1b>;
+ vdd-l8-supply = <&vreg_s1b>;
+ vdd-l9-l10-supply = <&vreg_s1b>;
+ vdd-l11-supply = <&vreg_s1b>;
+ vdd-l12-l14-supply = <&vreg_bob>;
+ vdd-l13-l16-supply = <&vreg_bob>;
+ vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "b";
+
+ vreg_s1b: smps1 {
+ regulator-name = "vreg_s1b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2080000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2b: smps2 {
+ regulator-name = "vreg_s2b";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3b: smps3 {
+ regulator-name = "vreg_s3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b: ldo2 {
+ regulator-name = "vreg_l2b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b: ldo3 {
+ regulator-name = "vreg_l3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b: ldo4 {
+ regulator-name = "vreg_l4b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b: ldo5 {
+ regulator-name = "vreg_l5b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b: ldo7 {
+ regulator-name = "vreg_l7b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b: ldo8 {
+ regulator-name = "vreg_l8b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b: ldo9 {
+ regulator-name = "vreg_l9b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b: ldo10 {
+ regulator-name = "vreg_l10b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b: ldo11 {
+ regulator-name = "vreg_l11b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b: ldo12 {
+ regulator-name = "vreg_l12b";
+ /*
+ * Skip voltage voting for UFS VCC.
+ */
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b: ldo13 {
+ regulator-name = "vreg_l13b";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b: ldo14 {
+ regulator-name = "vreg_l14b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b: ldo15 {
+ regulator-name = "vreg_l15b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b: ldo16 {
+ regulator-name = "vreg_l16b";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b: ldo17 {
+ regulator-name = "vreg_l17b";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b: ldo18 {
+ regulator-name = "vreg_l18b";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b: ldo19 {
+ regulator-name = "vreg_l19b";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20b: ldo20 {
+ regulator-name = "vreg_l20b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21b: ldo21 {
+ regulator-name = "vreg_l21b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l22b: ldo22 {
+ regulator-name = "vreg_l22b";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l23b: ldo23 {
+ regulator-name = "vreg_l23b";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3b>;
+ vdd-l3-supply = <&vreg_s3b>;
+
+ qcom,pmic-id = "c";
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <650000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmr735b-rpmh-regulators";
+
+ vdd-l1-l2-supply= <&vreg_s3b>;
+ vdd-l3-supply= <&vreg_s3b>;
+ vdd-l4-supply= <&vreg_s1b>;
+ vdd-l5-supply= <&vreg_s2b>;
+ vdd-l6-supply= <&vreg_s2b>;
+ vdd-l7-l8-supply= <&vreg_s2b>;
+ vdd-l9-supply= <&vreg_s3b>;
+ vdd-l10-supply= <&vreg_s1b>;
+ vdd-l11-supply= <&vreg_s3b>;
+ vdd-l12-supply= <&vreg_s3b>;
+
+ qcom,pmic-id = "f";
+
+ vreg_l1f: ldo1 {
+ regulator-name = "vreg_l1f";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f: ldo2 {
+ regulator-name = "vreg_l2f";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f: ldo3 {
+ regulator-name = "vreg_l3f";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f: ldo4 {
+ regulator-name = "vreg_l4f";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f: ldo5 {
+ regulator-name = "vreg_l5f";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f: ldo6 {
+ regulator-name = "vreg_l6f";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f: ldo7 {
+ regulator-name = "vreg_l7f";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8f: ldo8 {
+ regulator-name = "vreg_l8f";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9f: ldo9 {
+ regulator-name = "vreg_l9f";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10f: ldo10 {
+ regulator-name = "vreg_l10f";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11f: ldo11 {
+ regulator-name = "vreg_l11f";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <864000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ /* Disable for now so simple-framebuffer continues working */
+ status = "disabled";
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c1 {
+ /* Samsung NFC @ 0x27 */
+
+ status = "okay";
+};
+
+&i2c3 {
+ /* AW88261FCR amplifier (top) @ 0x34 */
+ /* AW88261FCR amplifier (bottom) @ 0x35 */
+
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_s1b>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+ pinctrl-names = "default";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1144000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1896000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+
+ /* VL53L3 ToF @ 0x29 */
+ /* AW86938FCR vibrator @ 0x5a */
+};
+
+&pm8550vs_d {
+ status = "disabled";
+};
+
+&pm8550vs_e {
+ status = "disabled";
+};
+
+&pm8550vs_g {
+ status = "disabled";
+};
+
+&pmiv0104_eusb2_repeater {
+ vdd18-supply = <&vreg_l7b>;
+ vdd3-supply = <&vreg_l17b>;
+
+ qcom,tune-res-fsdif = /bits/ 8 <0x5>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0x8>;
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x6>;
+};
+
+&pmr735b_gpios {
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+
+ s1j_enable_default: s1j-enable-default-state {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&pmxr2230_gpios {
+ volume_up_default: volume-up-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ };
+};
+
+&pmxr2230_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <350000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <400000>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm7635/fairphone/fp6/adsp.mbn",
+ "qcom/sm7635/fairphone/fp6/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm7635/fairphone/fp6/cdsp.mbn",
+ "qcom/sm7635/fairphone/fp6/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm7635/fairphone/fp6/modem.mbn";
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/sm7635/fairphone/fp6/wpss.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l13b>;
+ vqmmc-supply = <&vreg_l23b>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&spi0 {
+ /* Eswin EPH8621 touchscreen @ 0 */
+};
+
+&tlmm {
+ /*
+ * 8-11: Fingerprint SPI
+ * 13: NC
+ * 63-64: WLAN UART
+ */
+ gpio-reserved-ranges = <8 4>, <13 1>, <63 2>;
+
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "otg";
+
+ /* USB 2.0 only */
+ qcom,select-utmi-as-pipe-clk;
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l2b>;
+ vdda12-supply = <&vreg_l4b>;
+
+ phys = <&pmiv0104_eusb2_repeater>;
+
+ status = "okay";
+};
--
2.50.0On 6/25/25 11:23 AM, Luca Weiss wrote:
> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
> on the SM7635 SoC.
[...]
> + /* Dummy panel for simple-framebuffer dimension info */
> + panel: panel {
> + compatible = "boe,bj631jhm-t71-d900";
> + width-mm = <65>;
> + height-mm = <146>;
> + };
I haven't ran through all the prerequisite-xx-id, but have
you submitted a binding for this?
[...]
> + reserved-memory {
> + /*
> + * ABL is powering down display and controller if this node is
> + * not named exactly "splash_region".
> + */
> + splash_region@e3940000 {
> + reg = <0x0 0xe3940000 0x0 0x2b00000>;
> + no-map;
> + };
> + };
:/ maybe we can convince ABL not to do it..
[...]
> + vreg_l12b: ldo12 {
> + regulator-name = "vreg_l12b";
> + /*
> + * Skip voltage voting for UFS VCC.
> + */
Why so?
[...]
> +&gpi_dma0 {
> + status = "okay";
> +};
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
These can be enabled in SoC DTSI.. it's possible that the secure
configuration forbids access to one, but these are generally made
per-platform
[...]
> +&pm8550vs_d {
> + status = "disabled";
> +};
> +
> +&pm8550vs_e {
> + status = "disabled";
> +};
> +
> +&pm8550vs_g {
> + status = "disabled";
> +};
Hm... perhaps we should disable these by deafult
[...]
> +&pmr735b_gpios {
> + pm8008_reset_n_default: pm8008-reset-n-default-state {
> + pins = "gpio3";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + bias-pull-down;
> + };
> +
> + s1j_enable_default: s1j-enable-default-state {
> + pins = "gpio1";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + power-source = <0>;
> + bias-disable;
> + output-low;
> + };
ordering by pin ID makes more sense, here and in tlmm
(and is actually written down)
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes
[...]
> +&pon_resin {
> + linux,code = <KEY_VOLUMEDOWN>;
> + status = "okay";
\n before status consistently, please
[...]
> +&tlmm {
> + /*
> + * 8-11: Fingerprint SPI
> + * 13: NC
> + * 63-64: WLAN UART
> + */
> + gpio-reserved-ranges = <8 4>, <13 1>, <63 2>;
Please match the style in x1-crd.dtsi
[...]
> +&usb_1 {
> + dr_mode = "otg";
> +
> + /* USB 2.0 only */
Because there's no usb3phy description yet, or due to hw design?
Konrad
On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote:
> On 6/25/25 11:23 AM, Luca Weiss wrote:
>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
>> on the SM7635 SoC.
>
> [...]
>
>> + /* Dummy panel for simple-framebuffer dimension info */
>> + panel: panel {
>> + compatible = "boe,bj631jhm-t71-d900";
>> + width-mm = <65>;
>> + height-mm = <146>;
>> + };
>
> I haven't ran through all the prerequisite-xx-id, but have
> you submitted a binding for this?
Actually not, kind of forgot about this. I believe I can create a
(mostly?) complete binding for the panel, but this simple description
for only width-mm & height-mm will differ from the final one, which will
have the DSI port, pinctrl, reset-gpios and various supplies.
I think I'll just drop it from v2 and keep it locally only, to get the
simpledrm scaling right.
>
> [...]
>
>> + reserved-memory {
>> + /*
>> + * ABL is powering down display and controller if this node is
>> + * not named exactly "splash_region".
>> + */
>> + splash_region@e3940000 {
>> + reg = <0x0 0xe3940000 0x0 0x2b00000>;
>> + no-map;
>> + };
>> + };
>
> :/ maybe we can convince ABL not to do it..
Yes, we talked about that. I will look into getting "splash-region" and
"splash" also into the ABL (edk2) build for the phone. Still won't
resolve that for any other brand of devices.
>
> [...]
>
>> + vreg_l12b: ldo12 {
>> + regulator-name = "vreg_l12b";
>> + /*
>> + * Skip voltage voting for UFS VCC.
>> + */
>
> Why so?
From downstream:
/*
* This is for UFS Peripheral,which supports 2 variants
* UFS 3.1 ,and UFS 2.2 both require different voltages.
* Hence preventing voltage voting as per previous targets.
*/
I haven't (successfully) brought up UFS yet, so I haven't looked more
into that.
The storage on FP6 is UFS 3.1 though fwiw.
>
> [...]
>
>> +&gpi_dma0 {
>> + status = "okay";
>> +};
>> +
>> +&gpi_dma1 {
>> + status = "okay";
>> +};
>
> These can be enabled in SoC DTSI.. it's possible that the secure
> configuration forbids access to one, but these are generally made
> per-platform
Ack
>
> [...]
>
>> +&pm8550vs_d {
>> + status = "disabled";
>> +};
>> +
>> +&pm8550vs_e {
>> + status = "disabled";
>> +};
>> +
>> +&pm8550vs_g {
>> + status = "disabled";
>> +};
>
> Hm... perhaps we should disable these by deafult
Do you want me to do this in this patchset, or we clean this up later at
some point? I'd prefer not adding even more dependencies to my patch
collection right now.
>
> [...]
>
>> +&pmr735b_gpios {
>> + pm8008_reset_n_default: pm8008-reset-n-default-state {
>> + pins = "gpio3";
>> + function = PMIC_GPIO_FUNC_NORMAL;
>> + bias-pull-down;
>> + };
>> +
>> + s1j_enable_default: s1j-enable-default-state {
>> + pins = "gpio1";
>> + function = PMIC_GPIO_FUNC_NORMAL;
>> + power-source = <0>;
>> + bias-disable;
>> + output-low;
>> + };
>
> ordering by pin ID makes more sense, here and in tlmm
>
> (and is actually written down)
> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes
Ah, that's news to me. Thanks!
>
> [...]
>
>> +&pon_resin {
>> + linux,code = <KEY_VOLUMEDOWN>;
>> + status = "okay";
>
> \n before status consistently, please
Ack
>
> [...]
>
>> +&tlmm {
>> + /*
>> + * 8-11: Fingerprint SPI
>> + * 13: NC
>> + * 63-64: WLAN UART
>> + */
>> + gpio-reserved-ranges = <8 4>, <13 1>, <63 2>;
>
> Please match the style in x1-crd.dtsi
Ack
>
> [...]
>
>> +&usb_1 {
>> + dr_mode = "otg";
>> +
>> + /* USB 2.0 only */
>
> Because there's no usb3phy description yet, or due to hw design?
HW design. Funnily enough with clk_ignore_unused this property is not
needed, and USB(2.0) works fine then. Just when (I assume) the USB3
clock is turned off which the bootloader has enabled, USB stops working.
Regards
Luca
>
> Konrad
On 6/27/25 1:33 PM, Luca Weiss wrote:
> On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote:
>> On 6/25/25 11:23 AM, Luca Weiss wrote:
>>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
>>> on the SM7635 SoC.
>>
>> [...]
>>
>>> + /* Dummy panel for simple-framebuffer dimension info */
>>> + panel: panel {
>>> + compatible = "boe,bj631jhm-t71-d900";
>>> + width-mm = <65>;
>>> + height-mm = <146>;
>>> + };
>>
>> I haven't ran through all the prerequisite-xx-id, but have
>> you submitted a binding for this?
>
> Actually not, kind of forgot about this. I believe I can create a
> (mostly?) complete binding for the panel, but this simple description
> for only width-mm & height-mm will differ from the final one, which will
> have the DSI port, pinctrl, reset-gpios and various supplies.
>
> I think I'll just drop it from v2 and keep it locally only, to get the
> simpledrm scaling right.
Yeah I think that'd be best in general
>
>>
>> [...]
>>
>>> + reserved-memory {
>>> + /*
>>> + * ABL is powering down display and controller if this node is
>>> + * not named exactly "splash_region".
>>> + */
>>> + splash_region@e3940000 {
>>> + reg = <0x0 0xe3940000 0x0 0x2b00000>;
>>> + no-map;
>>> + };
>>> + };
>>
>> :/ maybe we can convince ABL not to do it..
>
> Yes, we talked about that. I will look into getting "splash-region" and
> "splash" also into the ABL (edk2) build for the phone. Still won't
> resolve that for any other brand of devices.
Gotta start small! Maybe framebuffer@ would be more """idiomatic"""
but potayto/potahto
>
>>
>> [...]
>>
>>> + vreg_l12b: ldo12 {
>>> + regulator-name = "vreg_l12b";
>>> + /*
>>> + * Skip voltage voting for UFS VCC.
>>> + */
>>
>> Why so?
>
> From downstream:
>
> /*
> * This is for UFS Peripheral,which supports 2 variants
> * UFS 3.1 ,and UFS 2.2 both require different voltages.
> * Hence preventing voltage voting as per previous targets.
> */
>
> I haven't (successfully) brought up UFS yet, so I haven't looked more
> into that.
>
> The storage on FP6 is UFS 3.1 though fwiw.
Hm.. can you check what debugfs says about the voltage at runtime
(on downstream)? I'd assume you won't be shipping two kinds anyway
[...]
>>> +&pm8550vs_d {
>>> + status = "disabled";
>>> +};
>>> +
>>> +&pm8550vs_e {
>>> + status = "disabled";
>>> +};
>>> +
>>> +&pm8550vs_g {
>>> + status = "disabled";
>>> +};
>>
>> Hm... perhaps we should disable these by deafult
>
> Do you want me to do this in this patchset, or we clean this up later at
> some point? I'd prefer not adding even more dependencies to my patch
> collection right now.
I can totally hear that..
Let's include it in this patchset, right before SoC addition
I don't think there's any pm8550vs users trying to get merged in
parallel so it should be OK
[...]
>>> +&usb_1 {
>>> + dr_mode = "otg";
>>> +
>>> + /* USB 2.0 only */
>>
>> Because there's no usb3phy description yet, or due to hw design?
>
> HW design. Funnily enough with clk_ignore_unused this property is not
> needed, and USB(2.0) works fine then. Just when (I assume) the USB3
> clock is turned off which the bootloader has enabled, USB stops working.
The USB controller has two possible clock sources: the PIPE_CLK that
the QMPPHY outputs, or the UTMI clock (qcom,select-utmi-as-pipe-clk).
Because you said there's no USB3, I'm assuming DP-over-Type-C won't
be a thing either? :(
Konrad
On Fri Jun 27, 2025 at 4:34 PM CEST, Konrad Dybcio wrote:
> On 6/27/25 1:33 PM, Luca Weiss wrote:
>> On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote:
>>> On 6/25/25 11:23 AM, Luca Weiss wrote:
>>>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
>>>> on the SM7635 SoC.
>>>
>>> [...]
>>>
>>>> + /* Dummy panel for simple-framebuffer dimension info */
>>>> + panel: panel {
>>>> + compatible = "boe,bj631jhm-t71-d900";
>>>> + width-mm = <65>;
>>>> + height-mm = <146>;
>>>> + };
>>>
>>> I haven't ran through all the prerequisite-xx-id, but have
>>> you submitted a binding for this?
>>
>> Actually not, kind of forgot about this. I believe I can create a
>> (mostly?) complete binding for the panel, but this simple description
>> for only width-mm & height-mm will differ from the final one, which will
>> have the DSI port, pinctrl, reset-gpios and various supplies.
>>
>> I think I'll just drop it from v2 and keep it locally only, to get the
>> simpledrm scaling right.
>
> Yeah I think that'd be best in general
Ack
>
>>
>>>
>>> [...]
>>>
>>>> + reserved-memory {
>>>> + /*
>>>> + * ABL is powering down display and controller if this node is
>>>> + * not named exactly "splash_region".
>>>> + */
>>>> + splash_region@e3940000 {
>>>> + reg = <0x0 0xe3940000 0x0 0x2b00000>;
>>>> + no-map;
>>>> + };
>>>> + };
>>>
>>> :/ maybe we can convince ABL not to do it..
>>
>> Yes, we talked about that. I will look into getting "splash-region" and
>> "splash" also into the ABL (edk2) build for the phone. Still won't
>> resolve that for any other brand of devices.
>
> Gotta start small! Maybe framebuffer@ would be more """idiomatic"""
> but potayto/potahto
I'll try and work on the edk2 patch early next week, so if you tell me
soon, I can add some other name. I don't want to include 500 different
names though. :)
>
>>
>>>
>>> [...]
>>>
>>>> + vreg_l12b: ldo12 {
>>>> + regulator-name = "vreg_l12b";
>>>> + /*
>>>> + * Skip voltage voting for UFS VCC.
>>>> + */
>>>
>>> Why so?
>>
>> From downstream:
>>
>> /*
>> * This is for UFS Peripheral,which supports 2 variants
>> * UFS 3.1 ,and UFS 2.2 both require different voltages.
>> * Hence preventing voltage voting as per previous targets.
>> */
>>
>> I haven't (successfully) brought up UFS yet, so I haven't looked more
>> into that.
>>
>> The storage on FP6 is UFS 3.1 though fwiw.
>
> Hm.. can you check what debugfs says about the voltage at runtime
> (on downstream)? I'd assume you won't be shipping two kinds anyway
This is very likely just from Qualcomm's baseline.
>
> [...]
>
>>>> +&pm8550vs_d {
>>>> + status = "disabled";
>>>> +};
>>>> +
>>>> +&pm8550vs_e {
>>>> + status = "disabled";
>>>> +};
>>>> +
>>>> +&pm8550vs_g {
>>>> + status = "disabled";
>>>> +};
>>>
>>> Hm... perhaps we should disable these by deafult
>>
>> Do you want me to do this in this patchset, or we clean this up later at
>> some point? I'd prefer not adding even more dependencies to my patch
>> collection right now.
>
> I can totally hear that..
>
> Let's include it in this patchset, right before SoC addition
> I don't think there's any pm8550vs users trying to get merged in
> parallel so it should be OK
Okay, can do. Disable all of them (_c, _d, _e, _g), and re-enable them
in current users? I assume there might also be boards that only have
e.g. _d and no _c.
>
> [...]
>
>>>> +&usb_1 {
>>>> + dr_mode = "otg";
>>>> +
>>>> + /* USB 2.0 only */
>>>
>>> Because there's no usb3phy description yet, or due to hw design?
>>
>> HW design. Funnily enough with clk_ignore_unused this property is not
>> needed, and USB(2.0) works fine then. Just when (I assume) the USB3
>> clock is turned off which the bootloader has enabled, USB stops working.
>
> The USB controller has two possible clock sources: the PIPE_CLK that
> the QMPPHY outputs, or the UTMI clock (qcom,select-utmi-as-pipe-clk).
So okay like this for you, for a USB2.0-only HW?
>
> Because you said there's no USB3, I'm assuming DP-over-Type-C won't
> be a thing either? :(
Yep. I'd have preferred USB3+DP as well since it's actually quite cool
to have with proper Linux. On Android, at least on older versions it's
barely usable imo. Can't even properly watch videos on the big screen
with that SW stack.
Regards
Luca
>
> Konrad
On 6/27/25 4:44 PM, Luca Weiss wrote:
> On Fri Jun 27, 2025 at 4:34 PM CEST, Konrad Dybcio wrote:
>> On 6/27/25 1:33 PM, Luca Weiss wrote:
>>> On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote:
>>>> On 6/25/25 11:23 AM, Luca Weiss wrote:
>>>>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
>>>>> on the SM7635 SoC.
>>>>
>>>> [...]
>>>>
>>>>> + /* Dummy panel for simple-framebuffer dimension info */
>>>>> + panel: panel {
>>>>> + compatible = "boe,bj631jhm-t71-d900";
>>>>> + width-mm = <65>;
>>>>> + height-mm = <146>;
>>>>> + };
>>>>
>>>> I haven't ran through all the prerequisite-xx-id, but have
>>>> you submitted a binding for this?
>>>
>>> Actually not, kind of forgot about this. I believe I can create a
>>> (mostly?) complete binding for the panel, but this simple description
>>> for only width-mm & height-mm will differ from the final one, which will
>>> have the DSI port, pinctrl, reset-gpios and various supplies.
>>>
>>> I think I'll just drop it from v2 and keep it locally only, to get the
>>> simpledrm scaling right.
>>
>> Yeah I think that'd be best in general
>
> Ack
[...]
>>>>> +&pm8550vs_d {
>>>>> + status = "disabled";
>>>>> +};
>>>>> +
>>>>> +&pm8550vs_e {
>>>>> + status = "disabled";
>>>>> +};
>>>>> +
>>>>> +&pm8550vs_g {
>>>>> + status = "disabled";
>>>>> +};
>>>>
>>>> Hm... perhaps we should disable these by deafult
>>>
>>> Do you want me to do this in this patchset, or we clean this up later at
>>> some point? I'd prefer not adding even more dependencies to my patch
>>> collection right now.
>>
>> I can totally hear that..
>>
>> Let's include it in this patchset, right before SoC addition
>> I don't think there's any pm8550vs users trying to get merged in
>> parallel so it should be OK
>
> Okay, can do. Disable all of them (_c, _d, _e, _g), and re-enable them
> in current users? I assume there might also be boards that only have
> e.g. _d and no _c.
I suppose it's only fair to do so, in line with
d37e2646c8a5 ("arm64: dts: qcom: x1e80100-pmics: Enable all SMB2360 separately")
>>>>> +&usb_1 {
>>>>> + dr_mode = "otg";
>>>>> +
>>>>> + /* USB 2.0 only */
>>>>
>>>> Because there's no usb3phy description yet, or due to hw design?
>>>
>>> HW design. Funnily enough with clk_ignore_unused this property is not
>>> needed, and USB(2.0) works fine then. Just when (I assume) the USB3
>>> clock is turned off which the bootloader has enabled, USB stops working.
>>
>> The USB controller has two possible clock sources: the PIPE_CLK that
>> the QMPPHY outputs, or the UTMI clock (qcom,select-utmi-as-pipe-clk).
>
> So okay like this for you, for a USB2.0-only HW?
Yeah, maybe change the comment to something like:
/* USB 2.0 only (RX/TX lanes physically not routed) */
to avoid getting this question asked again
>> Because you said there's no USB3, I'm assuming DP-over-Type-C won't
>> be a thing either? :(
>
> Yep. I'd have preferred USB3+DP as well since it's actually quite cool
> to have with proper Linux. On Android, at least on older versions it's
> barely usable imo. Can't even properly watch videos on the big screen
> with that SW stack.
Bummer! Not something we can change though :(
Konrad
On Fri Jun 27, 2025 at 5:34 PM CEST, Konrad Dybcio wrote:
> On 6/27/25 4:44 PM, Luca Weiss wrote:
>> On Fri Jun 27, 2025 at 4:34 PM CEST, Konrad Dybcio wrote:
>>> On 6/27/25 1:33 PM, Luca Weiss wrote:
>>>> On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote:
>>>>> On 6/25/25 11:23 AM, Luca Weiss wrote:
>>>>>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
>>>>>> on the SM7635 SoC.
>>>>>
>>>>> [...]
>>>>>
>>>>>> +&pm8550vs_d {
>>>>>> + status = "disabled";
>>>>>> +};
>>>>>> +
>>>>>> +&pm8550vs_e {
>>>>>> + status = "disabled";
>>>>>> +};
>>>>>> +
>>>>>> +&pm8550vs_g {
>>>>>> + status = "disabled";
>>>>>> +};
>>>>>
>>>>> Hm... perhaps we should disable these by deafult
>>>>
>>>> Do you want me to do this in this patchset, or we clean this up later at
>>>> some point? I'd prefer not adding even more dependencies to my patch
>>>> collection right now.
>>>
>>> I can totally hear that..
>>>
>>> Let's include it in this patchset, right before SoC addition
>>> I don't think there's any pm8550vs users trying to get merged in
>>> parallel so it should be OK
>>
>> Okay, can do. Disable all of them (_c, _d, _e, _g), and re-enable them
>> in current users? I assume there might also be boards that only have
>> e.g. _d and no _c.
>
> I suppose it's only fair to do so, in line with
>
> d37e2646c8a5 ("arm64: dts: qcom: x1e80100-pmics: Enable all SMB2360 separately")
Sounds good, I've prepared this change for v2.
>
>
>>>>>> +&usb_1 {
>>>>>> + dr_mode = "otg";
>>>>>> +
>>>>>> + /* USB 2.0 only */
>>>>>
>>>>> Because there's no usb3phy description yet, or due to hw design?
>>>>
>>>> HW design. Funnily enough with clk_ignore_unused this property is not
>>>> needed, and USB(2.0) works fine then. Just when (I assume) the USB3
>>>> clock is turned off which the bootloader has enabled, USB stops working.
>>>
>>> The USB controller has two possible clock sources: the PIPE_CLK that
>>> the QMPPHY outputs, or the UTMI clock (qcom,select-utmi-as-pipe-clk).
>>
>> So okay like this for you, for a USB2.0-only HW?
>
> Yeah, maybe change the comment to something like:
>
> /* USB 2.0 only (RX/TX lanes physically not routed) */
>
> to avoid getting this question asked again
Ack
/* USB 2.0 only, HW does not support USB 3.x */
Regards
Luca
>
>>> Because you said there's no USB3, I'm assuming DP-over-Type-C won't
>>> be a thing either? :(
>>
>> Yep. I'd have preferred USB3+DP as well since it's actually quite cool
>> to have with proper Linux. On Android, at least on older versions it's
>> barely usable imo. Can't even properly watch videos on the big screen
>> with that SW stack.
>
> Bummer! Not something we can change though :(
>
> Konrad
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