[v4] riscv: Add support for xmipsexectl

[PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

Posted by Aleksa Paunovic via B4 Relay 3 months, 2 weeks ago

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add MIPS.PAUSE instruction opcode. This instruction is a part of the
xmipsexectl vendor extension.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe95987105ed85a 100644
--- a/arch/riscv/include/asm/vendor_extensions/mips.h
+++ b/arch/riscv/include/asm/vendor_extensions/mips.h
@@ -13,4 +13,11 @@
 
 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
 
+/* MIPS.PAUSE is an alternative opcode which is implemented to have the */
+/* same behavior as PAUSE on some MIPS RISCV cores. */
+/* It is a ‘hint’ encoding of the SLLI instruction, */
+/* with rd = 0, rs1 = 0 and imm = 5. */
+
+#define MIPS_PAUSE	".4byte 0x00501013\n\t"
+
 #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H

-- 
2.34.1

Re: [PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

Posted by Alexandre Ghiti 2 months, 3 weeks ago

On 6/25/25 16:20, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Add MIPS.PAUSE instruction opcode. This instruction is a part of the
> xmipsexectl vendor extension.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
> index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe95987105ed85a 100644
> --- a/arch/riscv/include/asm/vendor_extensions/mips.h
> +++ b/arch/riscv/include/asm/vendor_extensions/mips.h
> @@ -13,4 +13,11 @@
>   
>   extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
>   
> +/* MIPS.PAUSE is an alternative opcode which is implemented to have the */
> +/* same behavior as PAUSE on some MIPS RISCV cores. */
> +/* It is a ‘hint’ encoding of the SLLI instruction, */
> +/* with rd = 0, rs1 = 0 and imm = 5. */


The comment block should have been like this:

/*
  * ...
  */


> +
> +#define MIPS_PAUSE	".4byte 0x00501013\n\t"
> +
>   #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
>

Unless there is something else to change in the following patches, no 
need to resend the whole patchset just to fix the comment block, I'll do 
it when I merge it.

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex