From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 617b9ec9eef1..68585ece796e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -208,6 +208,29 @@ sys: system-controller@10430000 {
resets = <&cpg 0x30>;
};
+ xspi: spi@11030000 {
+ compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
+ reg = <0 0x11030000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>;
+ reg-names = "regs", "dirmap";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "pulse", "err_pulse";
+ clocks = <&cpg CPG_MOD 0x9f>,
+ <&cpg CPG_MOD 0xa0>,
+ <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
+ <&cpg CPG_MOD 0xa1>;
+ clock-names = "ahb", "axi", "spi", "spix2";
+ assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
+ assigned-clock-rates = <133333334>;
+ resets = <&cpg 0xa3>, <&cpg 0xa4>;
+ reset-names = "hresetn", "aresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
ostm0: timer@11800000 {
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
reg = <0x0 0x11800000 0x0 0x1000>;
--
2.49.0Hi Prabhakar,
On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> @@ -208,6 +208,29 @@ sys: system-controller@10430000 {
> resets = <&cpg 0x30>;
> };
>
> + xspi: spi@11030000 {
> + compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
> + reg = <0 0x11030000 0 0x10000>,
> + <0 0x20000000 0 0x10000000>;
> + reg-names = "regs", "dirmap";
> + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "pulse", "err_pulse";
> + clocks = <&cpg CPG_MOD 0x9f>,
> + <&cpg CPG_MOD 0xa0>,
> + <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
> + <&cpg CPG_MOD 0xa1>;
> + clock-names = "ahb", "axi", "spi", "spix2";
> + assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
> + assigned-clock-rates = <133333334>;
Do you need these two properties?
If yes, perhaps they should be moved to the board part?
> + resets = <&cpg 0xa3>, <&cpg 0xa4>;
> + reset-names = "hresetn", "aresetn";
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> ostm0: timer@11800000 {
> compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
> reg = <0x0 0x11800000 0x0 0x1000>;
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Tue, Jul 1, 2025 at 1:07 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> > @@ -208,6 +208,29 @@ sys: system-controller@10430000 {
> > resets = <&cpg 0x30>;
> > };
> >
> > + xspi: spi@11030000 {
> > + compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
> > + reg = <0 0x11030000 0 0x10000>,
> > + <0 0x20000000 0 0x10000000>;
> > + reg-names = "regs", "dirmap";
> > + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "pulse", "err_pulse";
> > + clocks = <&cpg CPG_MOD 0x9f>,
> > + <&cpg CPG_MOD 0xa0>,
> > + <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
> > + <&cpg CPG_MOD 0xa1>;
> > + clock-names = "ahb", "axi", "spi", "spix2";
> > + assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
> > + assigned-clock-rates = <133333334>;
>
> Do you need these two properties?
> If yes, perhaps they should be moved to the board part?
Yes, I need the above two properties without it flash write operation
fails. Ok I will move them to board DTS.
Cheers,
Prabhakar
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