Add DT nodes for DPI to DSI Bridge and DSI Phy.
The DSI bridge is Cadence DSI and the PHY is a
Cadence DPHY with TI wrapper.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
.../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 363d68fec387..2413c4913a8b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2517,6 +2517,43 @@ watchdog18: watchdog@2550000 {
status = "reserved";
};
+ dphy_tx0: phy@4480000 {
+ compatible = "ti,j721e-dphy";
+ reg = <0x0 0x04480000 0x0 0x1000>;
+ clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 402 3>;
+ assigned-clock-parents = <&k3_clks 402 4>;
+ assigned-clock-rates = <19200000>;
+ status = "disabled";
+ };
+
+ dsi0: dsi@4800000 {
+ compatible = "ti,j721e-dsi";
+ reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
+ clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ dsi0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
mhdp: bridge@a000000 {
compatible = "ti,j721e-mhdp8546";
reg = <0x0 0xa000000 0x0 0x30a00>,
--
2.34.1Hi
On 24/06/25 13:56, Jayesh Choudhary wrote:
> Add DT nodes for DPI to DSI Bridge and DSI Phy.
> The DSI bridge is Cadence DSI and the PHY is a
> Cadence DPHY with TI wrapper.
>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index 363d68fec387..2413c4913a8b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -2517,6 +2517,43 @@ watchdog18: watchdog@2550000 {
> status = "reserved";
> };
>
> + dphy_tx0: phy@4480000 {
> + compatible = "ti,j721e-dphy";
> + reg = <0x0 0x04480000 0x0 0x1000>;
Follow the convention of the file. Use:
reg = <0x00 0x04480000 0x00 0x1000>;
Please fix throughout the series.
> + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
> + clock-names = "psm", "pll_ref";
> + #phy-cells = <0>;
> + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 402 3>;
> + assigned-clock-parents = <&k3_clks 402 4>;
> + assigned-clock-rates = <19200000>;
> + status = "disabled";
> + };
> +
> + dsi0: dsi@4800000 {
> + compatible = "ti,j721e-dsi";
> + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
> + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
> + clock-names = "dsi_p_clk", "dsi_sys_clk";
> + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
> + interrupt-parent = <&gic500>;
This is implied and can be dropped.
> + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&dphy_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> +
> + dsi0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + };
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> mhdp: bridge@a000000 {
> compatible = "ti,j721e-mhdp8546";
> reg = <0x0 0xa000000 0x0 0x30a00>,
--
Regards
Vignesh
https://ti.com/opensource
Hello Vignesh,
On 26/06/25 11:56, Vignesh Raghavendra wrote:
> Hi
>
> On 24/06/25 13:56, Jayesh Choudhary wrote:
>> Add DT nodes for DPI to DSI Bridge and DSI Phy.
>> The DSI bridge is Cadence DSI and the PHY is a
>> Cadence DPHY with TI wrapper.
>>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>> .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 37 +++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> index 363d68fec387..2413c4913a8b 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> @@ -2517,6 +2517,43 @@ watchdog18: watchdog@2550000 {
>> status = "reserved";
>> };
>>
>> + dphy_tx0: phy@4480000 {
>> + compatible = "ti,j721e-dphy";
>> + reg = <0x0 0x04480000 0x0 0x1000>;
>
> Follow the convention of the file. Use:
>
> reg = <0x00 0x04480000 0x00 0x1000>;
Okay I will add padding.
Will add it to 4th field as well as I am seeing it in some
nodes:
reg = <0x00 0x04480000 0x00 0x00001000>;
>
> Please fix throughout the series.
Okay.
>
>> + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
>> + clock-names = "psm", "pll_ref";
>> + #phy-cells = <0>;
>> + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 402 3>;
>> + assigned-clock-parents = <&k3_clks 402 4>;
>> + assigned-clock-rates = <19200000>;
>> + status = "disabled";
>> + };
>> +
>> + dsi0: dsi@4800000 {
>> + compatible = "ti,j721e-dsi";
>> + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
>> + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
>> + clock-names = "dsi_p_clk", "dsi_sys_clk";
>> + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
>
>> + interrupt-parent = <&gic500>;
>
> This is implied and can be dropped.
Will drop.
Warm Regards,
Jayesh
>
>> + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&dphy_tx0>;
>> + phy-names = "dphy";
>> + status = "disabled";
>> +
>> + dsi0_ports: ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + port@0 {
>> + reg = <0>;
>> + };
>> + port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> mhdp: bridge@a000000 {
>> compatible = "ti,j721e-mhdp8546";
>> reg = <0x0 0xa000000 0x0 0x30a00>,
>
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