[v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

[PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Kathiravan Thirumoorthy 3 months, 2 weeks ago

QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
first SE, which supports a 4-wire UART configuration suitable for
applications such as HS-UART.

Note that the required initialization for this SE is not handled by the
bootloader. Therefore, add the SE node in the device tree but keep it
disabled. Enable it once Linux gains support for configuring the SE,
allowing to use in relevant RDPs.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Changes in v2:
- Correct the interrupt number
- Link to v1: https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.qualcomm.com
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c189bafe690514 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -417,6 +417,15 @@ qupv3: geniqup@1ac0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 
+			uart0: serial@1a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x01a80000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_UART0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
 			uart1: serial@1a84000 {
 				compatible = "qcom,geni-debug-uart";
 				reg = <0 0x01a84000 0 0x4000>;

---
base-commit: f817b6dd2b62d921a6cdc0a3ac599cd1851f343c
change-id: 20250624-ipq5424_hsuart-8b136b39ca18

Best regards,
-- 
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>

Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Konrad Dybcio 3 months, 2 weeks ago

On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
> first SE, which supports a 4-wire UART configuration suitable for
> applications such as HS-UART.
> 
> Note that the required initialization for this SE is not handled by the
> bootloader. Therefore, add the SE node in the device tree but keep it
> disabled. Enable it once Linux gains support for configuring the SE,
> allowing to use in relevant RDPs.

Do you mean fw loading support?

> 
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> Changes in v2:
> - Correct the interrupt number
> - Link to v1: https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.qualcomm.com
> ---
>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c189bafe690514 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -417,6 +417,15 @@ qupv3: geniqup@1ac0000 {
>  			#address-cells = <2>;
>  			#size-cells = <2>;
>  
> +			uart0: serial@1a80000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0 0x01a80000 0 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_UART0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};

I'd normally expect to see a pin configuration here as well,
especially since you mention the bootloader doesn't configure
the interface

Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Kathiravan Thirumoorthy 3 months, 2 weeks ago

On 6/24/2025 8:08 PM, Konrad Dybcio wrote:
> On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
>> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
>> first SE, which supports a 4-wire UART configuration suitable for
>> applications such as HS-UART.
>>
>> Note that the required initialization for this SE is not handled by the
>> bootloader. Therefore, add the SE node in the device tree but keep it
>> disabled. Enable it once Linux gains support for configuring the SE,
>> allowing to use in relevant RDPs.
> Do you mean fw loading support?

SE0 is minicore, so we don't need to load the FW. But apart from FW , 
protocol specific configurations to be done in the SE's Image 
Configuration registers, which is taken care in the patch[1]

[1] [PATCH v5 0/5] Add support to load QUP SE firmware from 
<https://lore.kernel.org/linux-arm-msm/20250624095102.1587580-1-viken.dadhaniya@oss.qualcomm.com/T/#m37a6b739c66040cde5b6b0121a03da7ea6715842>

>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>> Changes in v2:
>> - Correct the interrupt number
>> - Link to v1: https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.qualcomm.com
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c189bafe690514 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -417,6 +417,15 @@ qupv3: geniqup@1ac0000 {
>>   			#address-cells = <2>;
>>   			#size-cells = <2>;
>>   
>> +			uart0: serial@1a80000 {
>> +				compatible = "qcom,geni-uart";
>> +				reg = <0 0x01a80000 0 0x4000>;
>> +				clocks = <&gcc GCC_QUPV3_UART0_CLK>;
>> +				clock-names = "se";
>> +				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
> I'd normally expect to see a pin configuration here as well,
> especially since you mention the bootloader doesn't configure
> the interface

Ack.

>
> Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Konrad Dybcio 3 months, 2 weeks ago

On 6/25/25 7:55 AM, Kathiravan Thirumoorthy wrote:
> 
> On 6/24/2025 8:08 PM, Konrad Dybcio wrote:
>> On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
>>> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
>>> first SE, which supports a 4-wire UART configuration suitable for
>>> applications such as HS-UART.
>>>
>>> Note that the required initialization for this SE is not handled by the
>>> bootloader. Therefore, add the SE node in the device tree but keep it
>>> disabled. Enable it once Linux gains support for configuring the SE,
>>> allowing to use in relevant RDPs.
>> Do you mean fw loading support?
> 
> SE0 is minicore, so we don't need to load the FW. But apart from FW , protocol specific configurations to be done in the SE's Image Configuration registers, which is taken care in the patch[1]
> 
> [1] [PATCH v5 0/5] Add support to load QUP SE firmware from <https://lore.kernel.org/linux-arm-msm/20250624095102.1587580-1-viken.dadhaniya@oss.qualcomm.com/T/#m37a6b739c66040cde5b6b0121a03da7ea6715842>

I've heard the 'minicore' or similar name before.. how does it differ
from a "normal" SE? (+Mukesh & Viken)

Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Kathiravan Thirumoorthy 3 months, 2 weeks ago

On 6/25/2025 5:44 PM, Konrad Dybcio wrote:
> On 6/25/25 7:55 AM, Kathiravan Thirumoorthy wrote:
>> On 6/24/2025 8:08 PM, Konrad Dybcio wrote:
>>> On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
>>>> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
>>>> first SE, which supports a 4-wire UART configuration suitable for
>>>> applications such as HS-UART.
>>>>
>>>> Note that the required initialization for this SE is not handled by the
>>>> bootloader. Therefore, add the SE node in the device tree but keep it
>>>> disabled. Enable it once Linux gains support for configuring the SE,
>>>> allowing to use in relevant RDPs.
>>> Do you mean fw loading support?
>> SE0 is minicore, so we don't need to load the FW. But apart from FW , protocol specific configurations to be done in the SE's Image Configuration registers, which is taken care in the patch[1]
>>
>> [1] [PATCH v5 0/5] Add support to load QUP SE firmware from <https://lore.kernel.org/linux-arm-msm/20250624095102.1587580-1-viken.dadhaniya@oss.qualcomm.com/T/#m37a6b739c66040cde5b6b0121a03da7ea6715842>
> I've heard the 'minicore' or similar name before.. how does it differ
> from a "normal" SE? (+Mukesh & Viken)

There are 2 types of SE. One is Minicore and another one is FW based.

Minicore SE supports only I2C / SPI / UART protocols and it is fixed in 
RTL. Depends on the protocol needed, we need to configure the "Image 
Configuration registers".

FW based SE supports wide variety of protocols like I3C, CAN and so on. 
This can be achieved by the loading the protocol specific FW image and 
configuring the "Image Configuration registers".

> Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE

Posted by Konrad Dybcio 3 months, 2 weeks ago

On 6/26/25 7:16 AM, Kathiravan Thirumoorthy wrote:
> 
> On 6/25/2025 5:44 PM, Konrad Dybcio wrote:
>> On 6/25/25 7:55 AM, Kathiravan Thirumoorthy wrote:
>>> On 6/24/2025 8:08 PM, Konrad Dybcio wrote:
>>>> On 6/24/25 11:00 AM, Kathiravan Thirumoorthy wrote:
>>>>> QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
>>>>> first SE, which supports a 4-wire UART configuration suitable for
>>>>> applications such as HS-UART.
>>>>>
>>>>> Note that the required initialization for this SE is not handled by the
>>>>> bootloader. Therefore, add the SE node in the device tree but keep it
>>>>> disabled. Enable it once Linux gains support for configuring the SE,
>>>>> allowing to use in relevant RDPs.
>>>> Do you mean fw loading support?
>>> SE0 is minicore, so we don't need to load the FW. But apart from FW , protocol specific configurations to be done in the SE's Image Configuration registers, which is taken care in the patch[1]
>>>
>>> [1] [PATCH v5 0/5] Add support to load QUP SE firmware from <https://lore.kernel.org/linux-arm-msm/20250624095102.1587580-1-viken.dadhaniya@oss.qualcomm.com/T/#m37a6b739c66040cde5b6b0121a03da7ea6715842>
>> I've heard the 'minicore' or similar name before.. how does it differ
>> from a "normal" SE? (+Mukesh & Viken)
> 
> There are 2 types of SE. One is Minicore and another one is FW based.
> 
> Minicore SE supports only I2C / SPI / UART protocols and it is fixed in RTL. Depends on the protocol needed, we need to configure the "Image Configuration registers".
> 
> FW based SE supports wide variety of protocols like I3C, CAN and so on. This can be achieved by the loading the protocol specific FW image and configuring the "Image Configuration registers".

Got it, thank you

Konrad