Add configuration for ethernet controller on Huashan Pi.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
index 26b57e15adc1..86f76159c304 100644
--- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
+++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
@@ -55,6 +55,16 @@ &emmc {
 	non-removable;
 };
 
+&gmac0 {
+	status = "okay";
+	phy-handle = <&internal_ephy>;
+	phy-mode = "internal";
+};
+
+&mdio {
+	status = "okay";
+};
+
 &sdhci0 {
 	status = "okay";
 	bus-width = <4>;
-- 
2.50.0

On Mon, Jun 23, 2025 at 08:30:46AM +0800, Inochi Amaoto wrote:
> Add configuration for ethernet controller on Huashan Pi.
> 
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> index 26b57e15adc1..86f76159c304 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> @@ -55,6 +55,16 @@ &emmc {
>  	non-removable;
>  };
>  
> +&gmac0 {
> +	status = "okay";
> +	phy-handle = <&internal_ephy>;
> +	phy-mode = "internal";
> +};

Since the PHY is internal, it should be part of the SoC .dtsi file,
same as any other peripheral. The board .dts file can then enable it.

    Andrew

---
pw-bot: cr

On Mon, Jun 23, 2025 at 09:26:43AM +0200, Andrew Lunn wrote:
> On Mon, Jun 23, 2025 at 08:30:46AM +0800, Inochi Amaoto wrote:
> > Add configuration for ethernet controller on Huashan Pi.
> > 
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> >  arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > index 26b57e15adc1..86f76159c304 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > @@ -55,6 +55,16 @@ &emmc {
> >  	non-removable;
> >  };
> >  
> > +&gmac0 {
> > +	status = "okay";
> > +	phy-handle = <&internal_ephy>;
> > +	phy-mode = "internal";
> > +};
> 
> Since the PHY is internal, it should be part of the SoC .dtsi file,
> same as any other peripheral. The board .dts file can then enable it.
> 

Does this mean only boards using external phy need to override the
"phy-handle" and "phy-mode"?

Regards,
Inochi