From: Ankit Agrawal <ankita@nvidia.com>
Fixes a security bug due to mismatched attributes between S1 and
S2 mapping.
Currently, it is possible for a region to be cacheable in the userspace
VMA, but mapped non cached in S2. This creates a potential issue where
the VMM may sanitize cacheable memory across VMs using cacheable stores,
ensuring it is zeroed. However, if KVM subsequently assigns this memory
to a VM as uncached, the VM could end up accessing stale, non-zeroed data
from a previous VM, leading to unintended data exposure. This is a security
risk.
Block such mismatch attributes case by returning EINVAL when userspace
try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*.
CC: Oliver Upton <oliver.upton@linux.dev>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Sean Christopherson <seanjc@google.com>
Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Ankit Agrawal <ankita@nvidia.com>
---
arch/arm64/kvm/mmu.c | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 5fe24f30999d..68c0f1c25dec 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1465,6 +1465,22 @@ static bool kvm_vma_mte_allowed(struct vm_area_struct *vma)
return vma->vm_flags & VM_MTE_ALLOWED;
}
+/*
+ * Determine the memory region cacheability from VMA's pgprot. This
+ * is used to set the stage 2 PTEs.
+ */
+static bool kvm_vma_is_cacheable(struct vm_area_struct *vma)
+{
+ switch (FIELD_GET(PTE_ATTRINDX_MASK, pgprot_val(vma->vm_page_prot))) {
+ case MT_NORMAL_NC:
+ case MT_DEVICE_nGnRnE:
+ case MT_DEVICE_nGnRE:
+ return false;
+ default:
+ return true;
+ }
+}
+
static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
struct kvm_s2_trans *nested,
struct kvm_memory_slot *memslot, unsigned long hva,
@@ -1472,7 +1488,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
{
int ret = 0;
bool write_fault, writable, force_pte = false;
- bool exec_fault, mte_allowed;
+ bool exec_fault, mte_allowed, is_vma_cacheable;
bool s2_force_noncacheable = false, vfio_allow_any_uc = false;
unsigned long mmu_seq;
phys_addr_t ipa = fault_ipa;
@@ -1617,6 +1633,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
vm_flags = vma->vm_flags;
+ is_vma_cacheable = kvm_vma_is_cacheable(vma);
+
/* Don't use the VMA after the unlock -- it may have vanished */
vma = NULL;
@@ -1660,6 +1678,14 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
writable = false;
}
+ /*
+ * Prohibit a region to be mapped non cacheable in S2 and marked as
+ * cacheabled in the userspace VMA. Such mismatched mapping is a
+ * security risk.
+ */
+ if (is_vma_cacheable && s2_force_noncacheable)
+ return -EINVAL;
+
if (exec_fault && s2_force_noncacheable)
return -ENOEXEC;
@@ -2219,6 +2245,12 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
ret = -EINVAL;
break;
}
+
+ /* Cacheable PFNMAP is not allowed */
+ if (kvm_vma_is_cacheable(vma)) {
+ ret = -EINVAL;
+ break;
+ }
}
hva = min(reg_end, vma->vm_end);
} while (hva < reg_end);
--
2.34.1On 21.06.25 06:21, ankita@nvidia.com wrote: > From: Ankit Agrawal <ankita@nvidia.com> > > Fixes a security bug due to mismatched attributes between S1 and > S2 mapping. > > Currently, it is possible for a region to be cacheable in the userspace > VMA, but mapped non cached in S2. This creates a potential issue where > the VMM may sanitize cacheable memory across VMs using cacheable stores, > ensuring it is zeroed. However, if KVM subsequently assigns this memory > to a VM as uncached, the VM could end up accessing stale, non-zeroed data > from a previous VM, leading to unintended data exposure. This is a security > risk. > > Block such mismatch attributes case by returning EINVAL when userspace > try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*. > > CC: Oliver Upton <oliver.upton@linux.dev> > CC: Catalin Marinas <catalin.marinas@arm.com> > CC: Sean Christopherson <seanjc@google.com> > Suggested-by: Jason Gunthorpe <jgg@nvidia.com> > Signed-off-by: Ankit Agrawal <ankita@nvidia.com> > --- Reviewed-by: David Hildenbrand <david@redhat.com> -- Cheers, David / dhildenb
On Sat, Jun 21, 2025 at 04:21:08AM +0000, ankita@nvidia.com wrote: > From: Ankit Agrawal <ankita@nvidia.com> > > Fixes a security bug due to mismatched attributes between S1 and > S2 mapping. > > Currently, it is possible for a region to be cacheable in the userspace > VMA, but mapped non cached in S2. This creates a potential issue where > the VMM may sanitize cacheable memory across VMs using cacheable stores, > ensuring it is zeroed. However, if KVM subsequently assigns this memory > to a VM as uncached, the VM could end up accessing stale, non-zeroed data > from a previous VM, leading to unintended data exposure. This is a security > risk. > > Block such mismatch attributes case by returning EINVAL when userspace > try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*. > > CC: Oliver Upton <oliver.upton@linux.dev> > CC: Catalin Marinas <catalin.marinas@arm.com> > CC: Sean Christopherson <seanjc@google.com> > Suggested-by: Jason Gunthorpe <jgg@nvidia.com> > Signed-off-by: Ankit Agrawal <ankita@nvidia.com> > --- > arch/arm64/kvm/mmu.c | 34 +++++++++++++++++++++++++++++++++- > 1 file changed, 33 insertions(+), 1 deletion(-) Looks straightforward now Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Jason
On Sat, Jun 21, 2025 at 04:21:08AM +0000, ankita@nvidia.com wrote:
> From: Ankit Agrawal <ankita@nvidia.com>
>
> Fixes a security bug due to mismatched attributes between S1 and
> S2 mapping.
>
> Currently, it is possible for a region to be cacheable in the userspace
> VMA, but mapped non cached in S2. This creates a potential issue where
> the VMM may sanitize cacheable memory across VMs using cacheable stores,
> ensuring it is zeroed. However, if KVM subsequently assigns this memory
> to a VM as uncached, the VM could end up accessing stale, non-zeroed data
> from a previous VM, leading to unintended data exposure. This is a security
> risk.
>
> Block such mismatch attributes case by returning EINVAL when userspace
> try to map PFNMAP cacheable. Only allow NORMAL_NC and DEVICE_*.
>
> CC: Oliver Upton <oliver.upton@linux.dev>
> CC: Catalin Marinas <catalin.marinas@arm.com>
> CC: Sean Christopherson <seanjc@google.com>
> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Ankit Agrawal <ankita@nvidia.com>
> ---
> arch/arm64/kvm/mmu.c | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
Sorry for the drive-by comment, but I was looking at this old series from
Paolo (look at the cover letter and patch 5):
https://lore.kernel.org/r/20250109133817.314401-1-pbonzini@redhat.com
in which he points out that the arm64 get_vma_page_shift() function
incorrectly assumes that a VM_PFNMAP VMA is physically contiguous, which
may not be the case if a driver calls remap_pfn_range() to mess around
with mappings within the VMA. I think that implies that the optimisation
in 2aa53d68cee6 ("KVM: arm64: Try stage2 block mapping for host device
MMIO") is unsound.
But it got me thinking -- given that remap_pfn_range() also takes a 'prot'
argument, how do we ensure that this is reflected in the guest? It feels
a bit dodgy to rely on drivers always passing 'vma->vm_page_prot'.
Will
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