From: Yicong Yang <yangyicong@hisilicon.com>

Support new version of DDRC/SLLC PMU identified with updated ACPI HID and
register definition. In order to support this, we do a preliminary refactor
to initialize device of each version by using driver data of each HID
rather than checking the version. This will also make the driver easier to
maintain and extend, since only the HID specific information along
with the new HID will be added to support the new version without touching
the common logic.

Two new Uncore PMU drivers is also added to support the monitoring the
events of the system bus (by NoC PMU) and the DVM operations (by MN PMU).

Change since v2:
- Rebase on 6.15-rc1, add Jonathan's tag.
Link: https://lore.kernel.org/linux-arm-kernel/20250321073846.23507-1-yangyicong@huawei.com/

Change since v1:
- Fold patch which extending the struct hisi_pmu_dev_info into its user
- Use bit shift rather than bit mask for SLLC PMU registers configuration
- Address other comments by Jonathan, thanks
Link: https://lore.kernel.org/linux-arm-kernel/20250218092000.41641-1-yangyicong@huawei.com/

Junhao He (6):
  drivers/perf: hisi: Simplify the probe process for each DDRC version
  drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
  drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU
    information
  drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
  drivers/perf: hisi: Relax the event number check of v2 PMUs
  drivers/perf: hisi: Add support for HiSilicon MN PMU driver

Yicong Yang (2):
  drivers/perf: hisi: Support PMUs with no interrupt
  drivers/perf: hisi: Add support for HiSilicon NoC PMU

 Documentation/admin-guide/perf/hisi-pmu.rst   |  11 +
 drivers/perf/hisilicon/Makefile               |   3 +-
 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 354 ++++++++--------
 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c  |   6 +-
 drivers/perf/hisilicon/hisi_uncore_mn_pmu.c   | 355 ++++++++++++++++
 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c  | 392 ++++++++++++++++++
 drivers/perf/hisilicon/hisi_uncore_pa_pmu.c   |   2 +-
 drivers/perf/hisilicon/hisi_uncore_pmu.c      |  11 +-
 drivers/perf/hisilicon/hisi_uncore_pmu.h      |   2 +
 drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 220 +++++++---
 10 files changed, 1098 insertions(+), 258 deletions(-)
 create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
 create mode 100644 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c

-- 
2.24.0

On Thu, 19 Jun 2025 20:55:49 +0800, Yicong Yang wrote:
> Support new version of DDRC/SLLC PMU identified with updated ACPI HID and
> register definition. In order to support this, we do a preliminary refactor
> to initialize device of each version by using driver data of each HID
> rather than checking the version. This will also make the driver easier to
> maintain and extend, since only the HID specific information along
> with the new HID will be added to support the new version without touching
> the common logic.
> 
> [...]

Applied first six patches to will (for-next/perf), thanks!

[1/8] drivers/perf: hisi: Simplify the probe process for each DDRC version
      https://git.kernel.org/will/c/dc86791ff68c
[2/8] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
      https://git.kernel.org/will/c/17aa34e86936
[3/8] drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information
      https://git.kernel.org/will/c/29614c55fe6f
[4/8] drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
      https://git.kernel.org/will/c/1fd20ba0a1dc
[5/8] drivers/perf: hisi: Relax the event number check of v2 PMUs
      https://git.kernel.org/will/c/35f5b36e8cc2
[6/8] drivers/perf: hisi: Support PMUs with no interrupt
      https://git.kernel.org/will/c/e480898e767c

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

Hi Will and Mark,

just want to make sure the mail's not lost somehow, it's been skipped for the last cycle and
no further comment since v2.

thanks.

On 2025/6/19 20:55, Yicong Yang wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
> 
> Support new version of DDRC/SLLC PMU identified with updated ACPI HID and
> register definition. In order to support this, we do a preliminary refactor
> to initialize device of each version by using driver data of each HID
> rather than checking the version. This will also make the driver easier to
> maintain and extend, since only the HID specific information along
> with the new HID will be added to support the new version without touching
> the common logic.
> 
> Two new Uncore PMU drivers is also added to support the monitoring the
> events of the system bus (by NoC PMU) and the DVM operations (by MN PMU).
> 
> Change since v2:
> - Rebase on 6.15-rc1, add Jonathan's tag.
> Link: https://lore.kernel.org/linux-arm-kernel/20250321073846.23507-1-yangyicong@huawei.com/
> 
> Change since v1:
> - Fold patch which extending the struct hisi_pmu_dev_info into its user
> - Use bit shift rather than bit mask for SLLC PMU registers configuration
> - Address other comments by Jonathan, thanks
> Link: https://lore.kernel.org/linux-arm-kernel/20250218092000.41641-1-yangyicong@huawei.com/
> 
> Junhao He (6):
>   drivers/perf: hisi: Simplify the probe process for each DDRC version
>   drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
>   drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU
>     information
>   drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
>   drivers/perf: hisi: Relax the event number check of v2 PMUs
>   drivers/perf: hisi: Add support for HiSilicon MN PMU driver
> 
> Yicong Yang (2):
>   drivers/perf: hisi: Support PMUs with no interrupt
>   drivers/perf: hisi: Add support for HiSilicon NoC PMU
> 
>  Documentation/admin-guide/perf/hisi-pmu.rst   |  11 +
>  drivers/perf/hisilicon/Makefile               |   3 +-
>  drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 354 ++++++++--------
>  drivers/perf/hisilicon/hisi_uncore_hha_pmu.c  |   6 +-
>  drivers/perf/hisilicon/hisi_uncore_mn_pmu.c   | 355 ++++++++++++++++
>  drivers/perf/hisilicon/hisi_uncore_noc_pmu.c  | 392 ++++++++++++++++++
>  drivers/perf/hisilicon/hisi_uncore_pa_pmu.c   |   2 +-
>  drivers/perf/hisilicon/hisi_uncore_pmu.c      |  11 +-
>  drivers/perf/hisilicon/hisi_uncore_pmu.h      |   2 +
>  drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 220 +++++++---
>  10 files changed, 1098 insertions(+), 258 deletions(-)
>  create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
>  create mode 100644 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
>

On Tue, 1 Jul 2025 20:36:11 +0800
Yicong Yang <yangyicong@huawei.com> wrote:

> Hi Will and Mark,
> 
> just want to make sure the mail's not lost somehow, it's been skipped for the last cycle and
> no further comment since v2.

Hi Will and Mark,

This one is still outstanding and Yicong mentioned some recent issues with
some Huawei emails being taken out by spam filters.  As such, a quick
ping from an account that shouldn't suffer that fate!

Jonathan

> 
> thanks.
> 
> On 2025/6/19 20:55, Yicong Yang wrote:
> > From: Yicong Yang <yangyicong@hisilicon.com>
> > 
> > Support new version of DDRC/SLLC PMU identified with updated ACPI HID and
> > register definition. In order to support this, we do a preliminary refactor
> > to initialize device of each version by using driver data of each HID
> > rather than checking the version. This will also make the driver easier to
> > maintain and extend, since only the HID specific information along
> > with the new HID will be added to support the new version without touching
> > the common logic.
> > 
> > Two new Uncore PMU drivers is also added to support the monitoring the
> > events of the system bus (by NoC PMU) and the DVM operations (by MN PMU).
> > 
> > Change since v2:
> > - Rebase on 6.15-rc1, add Jonathan's tag.
> > Link: https://lore.kernel.org/linux-arm-kernel/20250321073846.23507-1-yangyicong@huawei.com/
> > 
> > Change since v1:
> > - Fold patch which extending the struct hisi_pmu_dev_info into its user
> > - Use bit shift rather than bit mask for SLLC PMU registers configuration
> > - Address other comments by Jonathan, thanks
> > Link: https://lore.kernel.org/linux-arm-kernel/20250218092000.41641-1-yangyicong@huawei.com/
> > 
> > Junhao He (6):
> >   drivers/perf: hisi: Simplify the probe process for each DDRC version
> >   drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
> >   drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU
> >     information
> >   drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
> >   drivers/perf: hisi: Relax the event number check of v2 PMUs
> >   drivers/perf: hisi: Add support for HiSilicon MN PMU driver
> > 
> > Yicong Yang (2):
> >   drivers/perf: hisi: Support PMUs with no interrupt
> >   drivers/perf: hisi: Add support for HiSilicon NoC PMU
> > 
> >  Documentation/admin-guide/perf/hisi-pmu.rst   |  11 +
> >  drivers/perf/hisilicon/Makefile               |   3 +-
> >  drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 354 ++++++++--------
> >  drivers/perf/hisilicon/hisi_uncore_hha_pmu.c  |   6 +-
> >  drivers/perf/hisilicon/hisi_uncore_mn_pmu.c   | 355 ++++++++++++++++
> >  drivers/perf/hisilicon/hisi_uncore_noc_pmu.c  | 392 ++++++++++++++++++
> >  drivers/perf/hisilicon/hisi_uncore_pa_pmu.c   |   2 +-
> >  drivers/perf/hisilicon/hisi_uncore_pmu.c      |  11 +-
> >  drivers/perf/hisilicon/hisi_uncore_pmu.h      |   2 +
> >  drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 220 +++++++---
> >  10 files changed, 1098 insertions(+), 258 deletions(-)
> >  create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
> >  create mode 100644 drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
> >   
>

On Sun, Jul 13, 2025 at 05:27:32PM +0100, Jonathan Cameron wrote:
> On Tue, 1 Jul 2025 20:36:11 +0800
> Yicong Yang <yangyicong@huawei.com> wrote:
> 
> > just want to make sure the mail's not lost somehow, it's been skipped for the last cycle and
> > no further comment since v2.
> 
> This one is still outstanding and Yicong mentioned some recent issues with
> some Huawei emails being taken out by spam filters.  As such, a quick
> ping from an account that shouldn't suffer that fate!

No probs, it's on the backlog but we've got lots of patches and not many
reviewers :(

Thanks for checking, though.

Will