Add eMMC support for qcs8300 board.
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 21 ++++
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 113 ++++++++++++++++++++++
2 files changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
index 8c166ead912c..9c37a0f5ba25 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
@@ -17,6 +17,7 @@
aliases {
serial0 = &uart7;
+ mmc0 = &sdhc_1;
};
chosen {
@@ -332,6 +333,26 @@
status = "okay";
};
+&sdhc_1 {
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ vmmc-supply = <&vreg_l8a>;
+ vqmmc-supply = <&vreg_s4a>;
+
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ status = "okay";
+};
+
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 7ada029c32c1..98f023def05f 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -3837,6 +3837,69 @@
clock-names = "apb_pclk";
};
+ sdhc_1: mmc@87C4000 {
+ compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x87C4000 0x0 0x1000>,
+ <0x0 0x87C5000 0x0 0x1000>;
+ reg-names = "hc",
+ "cqhci";
+
+ interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ iommus = <&apps_smmu 0x0 0x0>;
+ interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ qcom,dll-config = <0x000F64EE>;
+ qcom,ddr-config = <0x80040868>;
+ supports-cqe;
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@@ -5042,6 +5105,56 @@
pins = "gpio13";
function = "qup2_se0";
};
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-bus-hold;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-bus-hold;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-bus-hold;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-bus-hold;
+ };
+ };
};
sram: sram@146d8000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative ProjectOn 6/19/25 9:02 AM, Sayali Lokhande wrote:
> Add eMMC support for qcs8300 board.
>
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> ---
It's customary to split board and SoC changes into separate commits
[...]
> + sdhc_1: mmc@87C4000 {
Please use lowercase hex across DT, in all places
> + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x87C4000 0x0 0x1000>,
To make it easier to compare by eye, we tend to pad the address
values to 8 hex digits with leading zeroes, please do so as well
> + <0x0 0x87C5000 0x0 0x1000>;
> + reg-names = "hc",
> + "cqhci";
> +
> + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq",
> + "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface",
> + "core",
> + "xo";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> + iommus = <&apps_smmu 0x0 0x0>;
In case anyone's wondering, this is actually the correct value
> + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "sdhc-ddr",
> + "cpu-sdhc";
[...]
> + sdc1_state_on: sdc1-on-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
Please move bias properties under drive-strength for consistency
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_state_off: sdc1-off-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-bus-hold;
Is bus-hold what we want here? Other platforms do a pull-up/down
or disable bias altogether
Konrad
On 6/23/2025 7:39 PM, Konrad Dybcio wrote:
> On 6/19/25 9:02 AM, Sayali Lokhande wrote:
>> Add eMMC support for qcs8300 board.
>>
>> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
>> ---
> It's customary to split board and SoC changes into separate commits
>
> [...]
>
>> + sdhc_1: mmc@87C4000 {
> Please use lowercase hex across DT, in all places
>
>> + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x0 0x87C4000 0x0 0x1000>,
> To make it easier to compare by eye, we tend to pad the address
> values to 8 hex digits with leading zeroes, please do so as well
Sure will do
>> + <0x0 0x87C5000 0x0 0x1000>;
>> + reg-names = "hc",
>> + "cqhci";
>> +
>> + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq",
>> + "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> + <&gcc GCC_SDCC1_APPS_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface",
>> + "core",
>> + "xo";
>> +
>> + resets = <&gcc GCC_SDCC1_BCR>;
>> +
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> + operating-points-v2 = <&sdhc1_opp_table>;
>> + iommus = <&apps_smmu 0x0 0x0>;
> In case anyone's wondering, this is actually the correct value
>
>> + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
>> + interconnect-names = "sdhc-ddr",
>> + "cpu-sdhc";
> [...]
>
>> + sdc1_state_on: sdc1-on-state {
>> + clk-pins {
>> + pins = "sdc1_clk";
>> + bias-disable;
>> + drive-strength = <16>;
> Please move bias properties under drive-strength for consistency
Will do
>
>> + };
>> +
>> + cmd-pins {
>> + pins = "sdc1_cmd";
>> + bias-pull-up;
>> + drive-strength = <10>;
>> + };
>> +
>> + data-pins {
>> + pins = "sdc1_data";
>> + bias-pull-up;
>> + drive-strength = <10>;
>> + };
>> +
>> + rclk-pins {
>> + pins = "sdc1_rclk";
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + sdc1_state_off: sdc1-off-state {
>> + clk-pins {
>> + pins = "sdc1_clk";
>> + bias-bus-hold;
> Is bus-hold what we want here? Other platforms do a pull-up/down
> or disable bias altogether
Yes we want bias-bus-hold, same as other qc platforms for example like
sc7280.dtsi
>
> Konrad
Hi Sayali, kernel test robot noticed the following build errors: [auto build test ERROR on robh/for-next] [also build test ERROR on linus/master v6.16-rc2 next-20250619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Sayali-Lokhande/arm64-dts-qcom-Add-eMMC-support-for-qcs8300/20250619-150421 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/20250619070224.23428-2-quic_sayalil%40quicinc.com patch subject: [PATCH V2 1/2] arm64: dts: qcom: Add eMMC support for qcs8300 config: arm64-randconfig-053-20250619 (https://download.01.org/0day-ci/archive/20250620/202506200608.fGUpDcoG-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.3.0 dtschema version: 2025.3.dev28+g49451a5 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250620/202506200608.fGUpDcoG-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202506200608.fGUpDcoG-lkp@intel.com/ All errors (new ones prefixed by >>): >> Error: arch/arm64/boot/dts/qcom/qcs8300.dtsi:3867.19-20 syntax error FATAL ERROR: Unable to parse input tree -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
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