arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++++++++++ 2 files changed, 32 insertions(+)
This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs. The cache configuration is described in datasheet chapter 15.2. Changelog: v1 -> v2: - Remove the cache-unified property from l1-cache node Mihai Sain (2): ARM: dts: microchip: sama7d65: Add cache configuration for cpu node ARM: dts: microchip: sama7g5: Add cache configuration for cpu node arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) base-commit: 52da431bf03b5506203bca27fe14a97895c80faf -- 2.50.0
On Wed, 18 Jun 2025 13:39:12 +0300, Mihai Sain wrote:
> This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs.
> The cache configuration is described in datasheet chapter 15.2.
>
> Changelog:
>
> v1 -> v2:
> - Remove the cache-unified property from l1-cache node
>
> Mihai Sain (2):
> ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
> ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
>
> arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++
> arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++++++++++
> 2 files changed, 32 insertions(+)
>
>
> base-commit: 52da431bf03b5506203bca27fe14a97895c80faf
> --
> 2.50.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit 52da431bf03b5506203bca27fe14a97895c80faf
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/microchip/' for 20250618103914.2712-1-mihai.sain@microchip.com:
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): 'cache-unified' is a required property
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
from schema $id: http://devicetree.org/schemas/cache.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: timer@e0800000 (atmel,sama5d2-tcb): clocks: [[2, 2, 91], [2, 2, 92], [2, 2, 93], [18, 1]] is too long
from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: timer@e0800000 (atmel,sama5d2-tcb): clocks: [[2, 2, 91], [2, 2, 92], [2, 2, 93], [17, 1]] is too long
from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: timer@e2814000 (atmel,sama5d2-tcb): clocks: [[2, 2, 88], [2, 2, 89], [2, 2, 90], [18, 1]] is too long
from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: timer@e2814000 (atmel,sama5d2-tcb): clocks: [[2, 2, 88], [2, 2, 89], [2, 2, 90], [17, 1]] is too long
from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
On Wed, Jun 18, 2025 at 08:36:25AM -0500, Rob Herring (Arm) wrote:
>
> On Wed, 18 Jun 2025 13:39:12 +0300, Mihai Sain wrote:
> > This patch series adds cache configuration for Microchip SAMA7D and SAMA7G MPUs.
> > The cache configuration is described in datasheet chapter 15.2.
> >
> > Changelog:
> >
> > v1 -> v2:
> > - Remove the cache-unified property from l1-cache node
> >
> > Mihai Sain (2):
> > ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
> > ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
> >
> > arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++
> > arch/arm/boot/dts/microchip/sama7g5.dtsi | 16 ++++++++++++++++
> > 2 files changed, 32 insertions(+)
> >
> >
> > base-commit: 52da431bf03b5506203bca27fe14a97895c80faf
> > --
> > 2.50.0
> >
> >
> >
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
> pip3 install dtschema --upgrade
>
>
> This patch series was applied (using b4) to base:
> Base: using specified base-commit 52da431bf03b5506203bca27fe14a97895c80faf
>
> If this is not the correct base, please add 'base-commit' tag
> (or use b4 which does this automatically)
>
> New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/microchip/' for 20250618103914.2712-1-mihai.sain@microchip.com:
>
> arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
> from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
> arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): 'cache-unified' is a required property
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
> from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): 'cache-unified' is a required property
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('l1-cache' was unexpected)
> from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): cache-level: 1 is less than the minimum of 2
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): 'cache-unified' is a required property
> from schema $id: http://devicetree.org/schemas/cache.yaml#
> arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dtb: l1-cache (cache): Unevaluated properties are not allowed ('cache-level', 'd-cache-size', 'i-cache-size', 'next-level-cache' were unexpected)
> from schema $id: http://devicetree.org/schemas/cache.yaml#
You are doing caches wrong as the schema is telling you.
The L1 caches are described in the CPU nodes, not a separate node. This
is detailed in the DT Spec as well.
Rob
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