Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch:
[    0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0

After this patch:
[root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
-r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified
-r--r--r-- 1 root root 6 Jun 17 11:39 compatible
-r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size
-r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size
-r--r--r-- 1 root root 9 Jun 17 11:39 name
-r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 phandle

[root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-size
-r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified
-r--r--r-- 1 root root 6 Jun 17 11:39 compatible
-r--r--r-- 1 root root 9 Jun 17 11:39 name
-r--r--r-- 1 root root 4 Jun 17 11:39 phandle

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index d08d773b1cc5..951d7af3ad1c 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -32,6 +32,23 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
 			clock-names = "cpu";
+			next-level-cache = <&L1>;
+
+			L1: l1-cache {
+				compatible = "cache";
+				cache-level = <1>;
+				d-cache-size = <32768>;
+				i-cache-size = <32768>;
+				cache-unified;
+				next-level-cache = <&L2>;
+			};
+
+			L2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-size = <262144>;
+				cache-unified;
+			};
 		};
 	};
 
-- 
2.49.0

Mihai,

On 17/06/2025 at 12:47, Mihai Sain wrote:
> Describe the cache memories according with datasheet chapter 15.2:
> - L1 cache configuration with 32KB for both data and instruction cache.
> - L2 cache configuration with 256KB unified cache.
> 
> Before this patch:
> [    0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0
> 
> After this patch:
> [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache
> -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
> -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified

Nope.

> -r--r--r-- 1 root root 6 Jun 17 11:39 compatible
> -r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size
> -r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size
> -r--r--r-- 1 root root 9 Jun 17 11:39 name
> -r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache
> -r--r--r-- 1 root root 4 Jun 17 11:39 phandle
> 
> [root@sama7d65eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache
> -r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
> -r--r--r-- 1 root root 4 Jun 17 11:39 cache-size
> -r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified
> -r--r--r-- 1 root root 6 Jun 17 11:39 compatible
> -r--r--r-- 1 root root 9 Jun 17 11:39 name
> -r--r--r-- 1 root root 4 Jun 17 11:39 phandle
> 
> Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
> ---
>   arch/arm/boot/dts/microchip/sama7d65.dtsi | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index d08d773b1cc5..951d7af3ad1c 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -32,6 +32,23 @@ cpu0: cpu@0 {
>   			device_type = "cpu";
>   			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
>   			clock-names = "cpu";
> +			next-level-cache = <&L1>;
> +
> +			L1: l1-cache {
> +				compatible = "cache";
> +				cache-level = <1>;
> +				d-cache-size = <32768>;
> +				i-cache-size = <32768>;
> +				cache-unified;

I don't think unified applied to L1 cache for C-A7.

Regards,
   Nicolas

> +				next-level-cache = <&L2>;
> +			};
> +
> +			L2: l2-cache {
> +				compatible = "cache";
> +				cache-level = <2>;
> +				cache-size = <262144>;
> +				cache-unified;
> +			};
>   		};
>   	};
>