From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add SMMU-V3 PMCG nodes for Agilex5.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 7d9394a04302..06920de87a41 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -133,6 +133,68 @@ usbphy0: usbphy {
 		compatible = "usb-nop-xceiv";
 	};
 
+	pmu0: pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu0_tcu: pmu@16002000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x16002000 0x0 0x1000>,
+			  <0x0 0x16022000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu0: pmu@16042000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x16042000 0x0 0x1000>,
+			  <0x0 0x16052000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu1: pmu@16062000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x16062000 0x0 0x1000>,
+			  <0x0 0x16072000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu2: pmu@16082000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x16082000 0x0 0x1000>,
+			  <0x0 0x16092000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu3: pmu@160a2000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x160A2000 0x0 0x1000>,
+			  <0x0 0x160B2000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu4: pmu@160c2000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x160C2000 0x0 0x1000>,
+			  <0x0 0x160D2000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pmu0_tbu5: pmu@160e2000 {
+		compatible = "arm,smmu-v3-pmcg";
+		reg = <0x0 0x160E2000 0x0 0x1000>,
+			  <0x0 0x160F2000 0x0 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0xffffffff>;
-- 
2.49.GIT

On 16/06/2025 16:50, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add SMMU-V3 PMCG nodes for Agilex5.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 7d9394a04302..06920de87a41 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -133,6 +133,68 @@ usbphy0: usbphy {
>  		compatible = "usb-nop-xceiv";
>  	};
>  
> +	pmu0: pmu {
> +		compatible = "arm,armv8-pmuv3";
> +		interrupt-parent = <&intc>;
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pmu0_tcu: pmu@16002000 {


It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.

Or... if it passes still obviously mixes MMIO and non-MMIO nodes. MMIO
nodes go into soc@0.

Best regards,
Krzysztof