On Tue, Aug 19, 2025 at 01:00:37AM +0200, Michael Riesch wrote:
> The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines.
> Add the variant and allow for the additional reset.
>
> Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
> ---
> .../bindings/phy/rockchip-inno-csi-dphy.yaml | 60 ++++++++++++++++++++--
> 1 file changed, 56 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> index 42da616ae2e3..10197cc9dc47 100644
> --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
> @@ -21,6 +21,7 @@ properties:
> - rockchip,rk3326-csi-dphy
> - rockchip,rk3368-csi-dphy
> - rockchip,rk3568-csi-dphy
> + - rockchip,rk3588-csi-dphy
>
> reg:
> maxItems: 1
> @@ -39,18 +40,50 @@ properties:
> maxItems: 1
>
> resets:
> - items:
> - - description: exclusive PHY reset line
> + minItems: 1
> + maxItems: 2
Add a description for the 2nd reset here.
>
> reset-names:
> - items:
> - - const: apb
> + minItems: 1
> + maxItems: 2
Add 'phy' to the list here and just minItems.
>
> rockchip,grf:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> Some additional phy settings are access through GRF regs.
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - rockchip,px30-csi-dphy
> + - rockchip,rk1808-csi-dphy
> + - rockchip,rk3326-csi-dphy
> + - rockchip,rk3368-csi-dphy
> + - rockchip,rk3568-csi-dphy
> + then:
> + properties:
> + resets:
> + items:
> + - description: exclusive PHY reset line
> +
> + reset-names:
> + items:
> + - const: apb
Then just 'maxItems: 1' here.
> + else:
> + properties:
> + resets:
> + items:
> + - description: APB reset line
> + - description: PHY reset line
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: phy
And 'minItems: 2' here.
> +
> required:
> - compatible
> - reg
> @@ -77,3 +110,22 @@ examples:
> reset-names = "apb";
> rockchip,grf = <&grf>;
> };
> + - |
> + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + phy@fedc0000 {
> + compatible = "rockchip,rk3588-csi-dphy";
> + reg = <0x0 0xfedc0000 0x0 0x8000>;
> + clocks = <&cru PCLK_CSIPHY0>;
> + clock-names = "pclk";
> + #phy-cells = <0>;
> + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
> + reset-names = "apb", "phy";
> + rockchip,grf = <&csidphy0_grf>;
> + };
> + };
>
> --
> 2.39.5
>