On 17/06/2025 10:54, Michael Riesch via B4 Relay wrote:
> From: Michael Riesch <michael.riesch@collabora.com>
>
> The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset
> value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF
> this offset is perfectly fine (in fact, register 0 is the only one in
> this register y
> file).
> Introduce a boolean variable to indicate valid registers and allow writes
> to register 0.
>
> Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> index 2ab99e1d47eb..75533d071025 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> @@ -87,10 +87,11 @@ struct dphy_reg {
> u32 offset;
> u32 mask;
> u32 shift;
> + u8 valid;
> };
>
> #define PHY_REG(_offset, _width, _shift) \
> - { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
> + { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, .valid = 1, }
>
> static const struct dphy_reg rk1808_grf_dphy_regs[] = {
> [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
> @@ -145,7 +146,7 @@ static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,
> const struct dphy_drv_data *drv_data = priv->drv_data;
> const struct dphy_reg *reg = &drv_data->grf_regs[index];
>
> - if (reg->offset)
> + if (reg->valid)
> regmap_write(priv->grf, reg->offset,
> HIWORD_UPDATE(value, reg->mask, reg->shift));
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>