Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.
This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/axiado/Makefile | 2 +
arch/arm64/boot/dts/axiado/ax3000.dtsi | 584 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/axiado/ax3000_evk.dts | 72 ++++
4 files changed, 659 insertions(+)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
subdir-y += apm
subdir-y += apple
subdir-y += arm
+subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..d5d84986d18efe9dfbb446ceee42fc4e4dbf95d0
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
+/ {
+ compatible = "axiado,ax3000";
+ interrupt-parent = <&gic500>;
+
+ aliases {
+ i3c0 = &i3c0;
+ i3c1 = &i3c1;
+ i3c2 = &i3c2;
+ i3c3 = &i3c3;
+ i3c4 = &i3c4;
+ i3c5 = &i3c5;
+ i3c6 = &i3c6;
+ i3c7 = &i3c7;
+ i3c8 = &i3c8;
+ i3c9 = &i3c9;
+ i3c10 = &i3c10;
+ i3c11 = &i3c11;
+ i3c12 = &i3c12;
+ i3c13 = &i3c13;
+ i3c14 = &i3c14;
+ i3c15 = &i3c15;
+ i3c16 = &i3c16;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-unified;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ timer:timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ clocks {
+ refclk: refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ ref_clk: ref_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_ahb: clk_ahb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_ahb";
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_xin";
+ };
+
+ clk_mali: clk_mali {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "clk_mali";
+ };
+
+ clk_pclk: clk_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ clock-output-names = "clk_pclk";
+ };
+
+ spi_clk: spi_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ apb_pclk: apb_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+ ranges;
+
+ gic500: interrupt-controller@80300000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ reg = <0x00 0x80300000 0x00 0x10000>,
+ <0x00 0x80380000 0x00 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ };
+
+ uart0: serial@80520000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80520000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart1: serial@805a0000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x805A0000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart2: serial@80620000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80620000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart3: serial@80520800 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80520800 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ /* GPIO Controller banks 0 - 7 */
+ gpio0: gpio-controller@80500000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80500000 0x00 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@80580000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80580000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@80600000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80600000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@80680000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80680000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@80700000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80700000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@80780000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80780000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@80800000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80800000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@80880000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80880000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ /* I3C Controller 0 - 16 */
+ i3c0: i3c@80500400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80500400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@80500800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80500800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@80580400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80580400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c3: i3c@80580800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80580800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c4: i3c@80600400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80600400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c5: i3c@80600800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80600800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c6: i3c@80680400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80680400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c7: i3c@80680800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80680800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c8: i3c@80700400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80700400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c9: i3c@80700800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80700800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c10: i3c@80780400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80780400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c11: i3c@80780800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80780800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c12: i3c@80800400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80800400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c13: i3c@80800800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80800800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c14: i3c@80880400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80880400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c15: i3c@80880800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80880800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c16: i3c@80620400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80620400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3000_evk.dts b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
new file mode 100644
index 0000000000000000000000000000000000000000..0a183695e857a3a1e722ea6b7bee388bf650f0a3
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+ model = "Axiado AX3000 EVK";
+ compatible = "axiado,ax3000_evk", "axiado,ax3000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ bootargs = "console=ttyPS3,115200 earlyprintk nr_cpus=4 earlycon";
+ stdout-path = "serial3:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* Cortex-A53 will use following memory map */
+ reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
+ <0x00000004 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
--
2.25.1
On Sun, Jun 15, 2025 at 11:32 PM Harshit Shah <hshah@axiado.com> wrote:
>
> Add initial device tree support for the AX3000 SoC and its evaluation
> platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
> Secure Vault, AI Engine and Firewall.
>
> This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
> controllers on the AX3000 evaluation board.
>
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/axiado/Makefile | 2 +
> arch/arm64/boot/dts/axiado/ax3000.dtsi | 584 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/axiado/ax3000_evk.dts | 72 ++++
> 4 files changed, 659 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
> subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> +subdir-y += axiado
> subdir-y += bitmain
> subdir-y += blaize
> subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb
> diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..d5d84986d18efe9dfbb446ceee42fc4e4dbf95d0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> @@ -0,0 +1,584 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
> +/ {
> + compatible = "axiado,ax3000";
Drop. As this is not valid and overridden anyways.
> + interrupt-parent = <&gic500>;
> +
> + aliases {
> + i3c0 = &i3c0;
> + i3c1 = &i3c1;
> + i3c2 = &i3c2;
> + i3c3 = &i3c3;
> + i3c4 = &i3c4;
> + i3c5 = &i3c5;
> + i3c6 = &i3c6;
> + i3c7 = &i3c7;
> + i3c8 = &i3c8;
> + i3c9 = &i3c9;
> + i3c10 = &i3c10;
> + i3c11 = &i3c11;
> + i3c12 = &i3c12;
> + i3c13 = &i3c13;
> + i3c14 = &i3c14;
> + i3c15 = &i3c15;
> + i3c16 = &i3c16;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x2>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-unified;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> + };
> +
> + timer:timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + arm,cpu-registers-not-fw-configured;
Drop. Not valid for arm64. And new platforms should fix the firmware anyways.
Rob
On 16/06/2025 06:31, Harshit Shah wrote: > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -9,6 +9,7 @@ subdir-y += amlogic > subdir-y += apm > subdir-y += apple > subdir-y += arm > +subdir-y += axiado > subdir-y += bitmain > subdir-y += blaize > subdir-y += broadcom > diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile > new file mode 100644 > index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160 > --- /dev/null > +++ b/arch/arm64/boot/dts/axiado/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb There is no such CONFIG symbol. Best regards, Krzysztof
Thank you Krzysztof for review. On 6/15/2025 11:10 PM, Krzysztof Kozlowski wrote: > On 16/06/2025 06:31, Harshit Shah wrote: >> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile >> >> +dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb > There is no such CONFIG symbol. Agree. I will keep Kconfig of the ARCH_AXIADO before this patch (and enable in defconfig in separate patch) > > Best regards, > Krzysztof Regards, Harshit.
On 16/06/2025 06:31, Harshit Shah wrote:
> Add initial device tree support for the AX3000 SoC and its evaluation
> platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
> Secure Vault, AI Engine and Firewall.
>
> This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
> controllers on the AX3000 evaluation board.
>
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/axiado/Makefile | 2 +
> arch/arm64/boot/dts/axiado/ax3000.dtsi | 584 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/axiado/ax3000_evk.dts | 72 ++++
> 4 files changed, 659 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
> subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> +subdir-y += axiado
> subdir-y += bitmain
> subdir-y += blaize
> subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb
> diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..d5d84986d18efe9dfbb446ceee42fc4e4dbf95d0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> @@ -0,0 +1,584 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
> +/ {
> + compatible = "axiado,ax3000";
> + interrupt-parent = <&gic500>;
> +
> + aliases {
> + i3c0 = &i3c0;
> + i3c1 = &i3c1;
> + i3c2 = &i3c2;
> + i3c3 = &i3c3;
> + i3c4 = &i3c4;
> + i3c5 = &i3c5;
> + i3c6 = &i3c6;
> + i3c7 = &i3c7;
> + i3c8 = &i3c8;
> + i3c9 = &i3c9;
> + i3c10 = &i3c10;
> + i3c11 = &i3c11;
> + i3c12 = &i3c12;
> + i3c13 = &i3c13;
> + i3c14 = &i3c14;
> + i3c15 = &i3c15;
> + i3c16 = &i3c16;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
None of these are properties of SoC, but board. Move respective aliases
to the board files.
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x2>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x3c0013a0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-unified;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> + };
> +
> + timer:timer {
Missing space before node name, but anyway label is unused.
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + clocks {
Keep proper sorting of nodes, see DTS coding style.
> + refclk: refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + ref_clk: ref_clk {
This makes no sense. You have refclk and ref_clk. These ARE THE SAME.
Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <1>;
> + };
> +
> + clk_ahb: clk_ahb {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "clk_ahb";
> + };
> +
> + clk_xin: clk_xin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + clock-output-names = "clk_xin";
> + };
> +
> + clk_mali: clk_mali {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <500000000>;
> + clock-output-names = "clk_mali";
> + };
> +
> + clk_pclk: clk_pclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <74250000>;
> + clock-output-names = "clk_pclk";
> + };
> +
> + spi_clk: spi_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + apb_pclk: apb_pclk {
No underscores in node names, but all these look incorrect - don't you
have clock controller?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic500>;
> + ranges;
> +
> + gic500: interrupt-controller@80300000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + reg = <0x00 0x80300000 0x00 0x10000>,
> + <0x00 0x80380000 0x00 0x80000>;
DTS coding style, incorrect order.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + };
> +
> + uart0: serial@80520000 {
> + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x00 0x80520000 0x00 0x100>;
DTS coding style.
> + clock-names = "uart_clk", "pclk";
> + clocks = <&refclk &refclk>;
> + status = "disabled";
> + };
> +
> + uart1: serial@805a0000 {
> + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x00 0x805A0000 0x00 0x100>;
> + clock-names = "uart_clk", "pclk";
> + clocks = <&refclk &refclk>;
> + status = "disabled";
> + };
> +
> + uart2: serial@80620000 {
> + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x00 0x80620000 0x00 0x100>;
> + clock-names = "uart_clk", "pclk";
> + clocks = <&refclk &refclk>;
> + status = "disabled";
> + };
> +
> + uart3: serial@80520800 {
> + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x00 0x80520800 0x00 0x100>;
> + clock-names = "uart_clk", "pclk";
> + clocks = <&refclk &refclk>;
> + status = "disabled";
> + };
> +
> + /* GPIO Controller banks 0 - 7 */
> + gpio0: gpio-controller@80500000 {
> + compatible = "cdns,gpio-r1p02";
> + clocks = <&refclk>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x00 0x80500000 0x00 0x400>;
DTS coding style.
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + status = "disabled";
> + };
> +
...
> + i3c14: i3c@80880400 {
> + compatible = "cdns,i3c-master";
> + clocks = <&refclk &clk_xin>;
> + clock-names = "pclk", "sysclk";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + i2c-scl-hz = <100000>;
> + i3c-scl-hz = <400000>;
> + reg = <0x00 0x80880400 0x00 0x400>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i3c15: i3c@80880800 {
> + compatible = "cdns,i3c-master";
> + clocks = <&refclk &clk_xin>;
> + clock-names = "pclk", "sysclk";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> + i2c-scl-hz = <100000>;
> + i3c-scl-hz = <400000>;
> + reg = <0x00 0x80880800 0x00 0x400>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i3c16: i3c@80620400 {
> + compatible = "cdns,i3c-master";
> + clocks = <&refclk &clk_xin>;
> + clock-names = "pclk", "sysclk";
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + i2c-scl-hz = <100000>;
> + i3c-scl-hz = <400000>;
> + reg = <0x00 0x80620400 0x00 0x400>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
Drop stray blank lines.
> + };
> +};
> diff --git a/arch/arm64/boot/dts/axiado/ax3000_evk.dts b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..0a183695e857a3a1e722ea6b7bee388bf650f0a3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
> @@ -0,0 +1,72 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ax3000.dtsi"
> +
> +/ {
> + model = "Axiado AX3000 EVK";
> + compatible = "axiado,ax3000_evk", "axiado,ax3000";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen {
> + bootargs = "console=ttyPS3,115200 earlyprintk nr_cpus=4 earlycon";
Drop bootargs. Not needed and not suitable for mainline. earlycon (not
earlyprintk!) is debugging tool, not wide mainline usage.
Best regards,
Krzysztof
Hi Krzysztof,
Thank you very much for the reviews.
On 6/15/2025 11:09 PM, Krzysztof Kozlowski wrote:
> On 16/06/2025 06:31, Harshit Shah wrote:
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> None of these are properties of SoC, but board. Move respective aliases
> to the board files.
Make sense. I will move it to the board file. Also I will only keep that
we use in the board file.
>> +
>> + timer:timer {
> Missing space before node name, but anyway label is unused.
Noted.
>> + compatible = "arm,armv8-timer";
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + arm,cpu-registers-not-fw-configured;
>> + };
>> +
>> + clocks {
> Keep proper sorting of nodes, see DTS coding style.
Ah, we missed that. thank you. I will keep the nodes as per the
alphabetical order.
=====
cpus
clocks
soc {
gic
gpios
i3cs
uarts
}
timer
=====
>> + refclk: refclk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + ref_clk: ref_clk {
> This makes no sense. You have refclk and ref_clk. These ARE THE SAME.
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
Thank you for the document, we will follow this document and will remove
redundant nodes.
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <1>;
>> + };
>> +
>> + spi_clk: spi_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <25000000>;
>> + };
>> +
>> + apb_pclk: apb_pclk {
> No underscores in node names, but all these look incorrect - don't you
> have clock controller?
Noted, we will remove the "_" from the nodes. We do have clock
controller however that is being accessed by other CPU before Linux will
come-up.
So, the purpose of this clock nodes is to calculate the frequencies for
other peripherals. (We will update the nodes with clock-<freq>)
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <25000000>;
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-parent = <&gic500>;
>> + ranges;
>> +
>> + gic500: interrupt-controller@80300000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + reg = <0x00 0x80300000 0x00 0x10000>,
>> + <0x00 0x80380000 0x00 0x80000>;
> DTS coding style, incorrect order.
Thank you, we are following this reference:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml?h=v6.11-rc1#n242
gic500: interrupt-controller@80300000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
reg = <0x00 0x80300000 0x00 0x10000>,
<0x00 0x80380000 0x00 0x80000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + };
>> +
>> + uart0: serial@80520000 {
>> + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x00 0x80520000 0x00 0x100>;
> DTS coding style.
Got it. Will move "reg = " in the second line.
>
>> +
>> +
>> + /* GPIO Controller banks 0 - 7 */
>> + gpio0: gpio-controller@80500000 {
>> + compatible = "cdns,gpio-r1p02";
>> + clocks = <&refclk>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x00 0x80500000 0x00 0x400>;
> DTS coding style.
Noted, will update on this and other nodes.
>
>
>
>
>> +
>> + status = "disabled";
>> + };
>> +
>> + i3c16: i3c@80620400 {
>> + compatible = "cdns,i3c-master";
>> + clocks = <&refclk &clk_xin>;
>> + clock-names = "pclk", "sysclk";
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> + i2c-scl-hz = <100000>;
>> + i3c-scl-hz = <400000>;
>> + reg = <0x00 0x80620400 0x00 0x400>;
>> + #address-cells = <3>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>> +
> Drop stray blank lines.
Okay, make sense.
>
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/axiado/ax3000_evk.dts b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
>>
>> +
>> + chosen {
>> + bootargs = "console=ttyPS3,115200 earlyprintk nr_cpus=4 earlycon";
> Drop bootargs. Not needed and not suitable for mainline. earlycon (not
> earlyprintk!) is debugging tool, not wide mainline usage.
Make sense. I will remove the bootargs.
> Best regards,
> Krzysztof
Regards,
Harshit.
On 20/06/2025 00:41, Harshit Shah wrote:
>>> +
>>> + spi_clk: spi_clk {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <25000000>;
>>> + };
>>> +
>>> + apb_pclk: apb_pclk {
>> No underscores in node names, but all these look incorrect - don't you
>> have clock controller?
> Noted, we will remove the "_" from the nodes. We do have clock
> controller however that is being accessed by other CPU before Linux will
> come-up.
What does it mean? Is the clock controller not available at all for
Linux or any other OS?
>
> So, the purpose of this clock nodes is to calculate the frequencies for
> other peripherals. (We will update the nodes with clock-<freq>)
You do not calculate any frequencies here... You created nodes for fixed
clocks but I question here whether these are fixed clocks.
Where are these clocks located exactly?
Best regards,
Krzysztof
On 6/19/2025 11:08 PM, Krzysztof Kozlowski wrote:
>>>> +
>>>> + spi_clk: spi_clk {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <25000000>;
>>>> + };
>>>> +
>>>> + apb_pclk: apb_pclk {
>>> No underscores in node names, but all these look incorrect - don't you
>>> have clock controller?
>> Noted, we will remove the "_" from the nodes. We do have clock
>> controller however that is being accessed by other CPU before Linux will
>> come-up.
> What does it mean? Is the clock controller not available at all for
> Linux or any other OS?
Apologies for the confusion. Yes, clock controller is available however
it is only accessible by another CPU which boots up before Linux comes up.
This another CPU is setting up the various output clocks (& PLLs) before
the Linux comes up.
So, that's the reason haven not added the clock controller in this DTS
but only will add fixed clocks.
>
>> So, the purpose of this clock nodes is to calculate the frequencies for
>> other peripherals. (We will update the nodes with clock-<freq>)
> You do not calculate any frequencies here... You created nodes for fixed
> clocks but I question here whether these are fixed clocks.
>
> Where are these clocks located exactly?
Yes, those clocks are fixed clocks, as it is being controlled by other
CPU and coming to A53 as fixed clocks.
I will take care of the format in the next revision.
>
>
> Best regards,
> Krzysztof
On 20/06/2025 23:18, Harshit Shah wrote:
> On 6/19/2025 11:08 PM, Krzysztof Kozlowski wrote:
>>>>> +
>>>>> + spi_clk: spi_clk {
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <25000000>;
>>>>> + };
>>>>> +
>>>>> + apb_pclk: apb_pclk {
>>>> No underscores in node names, but all these look incorrect - don't you
>>>> have clock controller?
>>> Noted, we will remove the "_" from the nodes. We do have clock
>>> controller however that is being accessed by other CPU before Linux will
>>> come-up.
>> What does it mean? Is the clock controller not available at all for
>> Linux or any other OS?
>
> Apologies for the confusion. Yes, clock controller is available however
> it is only accessible by another CPU which boots up before Linux comes up.
>
> This another CPU is setting up the various output clocks (& PLLs) before
> the Linux comes up.
>
> So, that's the reason haven not added the clock controller in this DTS
> but only will add fixed clocks.
And what happens if that other part decides to change frequencies?
Best regards,
Krzysztof
On 6/22/2025 2:49 AM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 20/06/2025 23:18, Harshit Shah wrote:
>> On 6/19/2025 11:08 PM, Krzysztof Kozlowski wrote:
>>>>>> +
>>>>>> + spi_clk: spi_clk {
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <25000000>;
>>>>>> + };
>>>>>> +
>>>>>> + apb_pclk: apb_pclk {
>>>>> No underscores in node names, but all these look incorrect - don't you
>>>>> have clock controller?
>>>> Noted, we will remove the "_" from the nodes. We do have clock
>>>> controller however that is being accessed by other CPU before Linux will
>>>> come-up.
>>> What does it mean? Is the clock controller not available at all for
>>> Linux or any other OS?
>> Apologies for the confusion. Yes, clock controller is available however
>> it is only accessible by another CPU which boots up before Linux comes up.
>>
>> This another CPU is setting up the various output clocks (& PLLs) before
>> the Linux comes up.
>>
>> So, that's the reason haven not added the clock controller in this DTS
>> but only will add fixed clocks.
> And what happens if that other part decides to change frequencies?
Good question. The current list of the peripheral in the device tree are
using the clock those are constant and can not be changed.
So, I am planning to add only following as a part of this patchset.
clocks {
clk_xin: clock-200000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "clk_xin";
};
refclk: clock-125000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
Later, we will add more patches as a part of next-separate series for
the controller, clocks(those can change) and other peripherals.
Is this okay that I keep only above fixed clock entries for this initial
patch-set?
>
> Best regards,
> Krzysztof
Regards,
Harshit.
On 23/06/2025 07:56, Harshit Shah wrote:
> So, I am planning to add only following as a part of this patchset.
>
> clocks {
> clk_xin: clock-200000000 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <200000000>;
> clock-output-names = "clk_xin";
> };
> refclk: clock-125000000 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <125000000>;
> };
> };
>
> Later, we will add more patches as a part of next-separate series for
> the controller, clocks(those can change) and other peripherals.
Yes
Best regards,
Krzysztof
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