From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reorder the `extal_clk` node in the RZ/T2H SoC DTSI to maintain
consistent sorting by node name.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 7a79db19aac6..1508f581cb66 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -13,13 +13,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -64,6 +57,13 @@ cpu3: cpu@300 {
};
};
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.49.0