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[PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes

Pritam Manohar Sutar posted 9 patches 3 months, 4 weeks ago
There is a newer version of this series
[PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes
Posted by Pritam Manohar Sutar 3 months, 4 weeks ago 
Add USB controller and USB PHY controller nodes for this SoC.

The USB controller has following features:
* Dual Role Device (DRD) controller
* DWC3 compatible
* Supports USB 3.0 host and USB 3.0 device interfaces but phy
  controller capability is limited to USB 2.0.
* Supports  full-speed (12 Mbps) and high-speed (480 Mbps) modes with
  USB device 2.0 interface
* Supports on-chip USB PHY transceiver
* Supports up to 16 bi-directional endpoints (that includes control
  endpoint 0)
* Complies with xHCI 1.1 specification

Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
 .../boot/dts/exynos/exynosautov920-sadk.dts   |  37 ++++++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 108 ++++++++++++++++++
 2 files changed, 145 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index a397f068ed53..984e899a2ebf 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -86,3 +86,40 @@ &usi_0 {
 &xtcxo {
 	clock-frequency = <38400000>;
 };
+
+/* usb */
+&usbdrd20_phy0 {
+	status = "okay";
+};
+
+&usbdrd20_dwc3_0 {
+	dr_mode = "peripheral";
+};
+
+&usbdrd20_0 {
+	status = "okay";
+};
+
+&usbdrd20_phy1 {
+	status = "okay";
+};
+
+&usbdrd20_dwc3_1 {
+	dr_mode = "peripheral";
+};
+
+&usbdrd20_1 {
+	status = "okay";
+};
+
+&usbdrd20_phy2 {
+	status = "okay";
+};
+
+&usbdrd20_dwc3_2 {
+	dr_mode = "peripheral";
+};
+
+&usbdrd20_2 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 2cb8041c8a9f..b1a9d1da47f6 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1048,6 +1048,114 @@ pinctrl_hsi1: pinctrl@16450000 {
 			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		usbdrd20_phy0: phy@16500000 {
+			compatible = "samsung,exynosautov920-usbdrd-phy";
+			reg = <0x16500000 0x0200>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "phy", "ref";
+			#phy-cells = <1>;
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			status = "disabled";
+		};
+
+		usbdrd20_phy1: phy@16510000 {
+			compatible = "samsung,exynosautov920-usbdrd-phy";
+			reg = <0x16510000 0x0200>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "phy", "ref";
+			#phy-cells = <1>;
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			status = "disabled";
+		};
+
+		usbdrd20_phy2: phy@16520000 {
+			compatible = "samsung,exynosautov920-usbdrd-phy";
+			reg = <0x16520000 0x0200>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "phy", "ref";
+			#phy-cells = <1>;
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			status = "disabled";
+		};
+
+		usbdrd20_0: usb@16700000 {
+			compatible = "samsung,exynosautov920-dwusb3";
+			ranges = <0x0 0x16700000 0x10000>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "ref", "susp_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+
+			usbdrd20_dwc3_0: usb@0 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x10000>;
+				clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+					 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+				clock-names = "ref", "susp_clk";
+				interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usbdrd20_phy0 0>;
+				phy-names = "usb2-phy";
+				snps,has-lpm-erratum;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		usbdrd20_1: usb@16800000 {
+			compatible = "samsung,exynosautov920-dwusb3";
+			ranges = <0x0 0x16800000 0x10000>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "ref", "susp_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+
+			usbdrd20_dwc3_1: usb@0 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x10000>;
+				clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+					 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+				clock-names = "ref", "susp_clk";
+				interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usbdrd20_phy1 0>;
+				phy-names = "usb2-phy";
+				snps,has-lpm-erratum;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		usbdrd20_2: usb@16900000 {
+			compatible = "samsung,exynosautov920-dwusb3";
+			ranges = <0x0 0x16900000 0x10000>;
+			clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+				 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+			clock-names = "ref", "susp_clk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+
+			usbdrd20_dwc3_2: usb@0 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x10000>;
+				clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+					 <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+				clock-names = "ref", "susp_clk";
+				interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usbdrd20_phy2 0>;
+				phy-names = "usb2-phy";
+				snps,has-lpm-erratum;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
 		pinctrl_hsi2: pinctrl@16c10000 {
 			compatible = "samsung,exynosautov920-pinctrl";
 			reg = <0x16c10000 0x10000>;
-- 
2.34.1
Re: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes
Posted by Krzysztof Kozlowski 3 months, 3 weeks ago 
On Fri, Jun 13, 2025 at 11:26:07AM GMT, Pritam Manohar Sutar wrote:
> Add USB controller and USB PHY controller nodes for this SoC.
> 
> The USB controller has following features:
> * Dual Role Device (DRD) controller
> * DWC3 compatible
> * Supports USB 3.0 host and USB 3.0 device interfaces but phy
>   controller capability is limited to USB 2.0.
> * Supports  full-speed (12 Mbps) and high-speed (480 Mbps) modes with
>   USB device 2.0 interface
> * Supports on-chip USB PHY transceiver
> * Supports up to 16 bi-directional endpoints (that includes control
>   endpoint 0)
> * Complies with xHCI 1.1 specification
> 
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> ---
>  .../boot/dts/exynos/exynosautov920-sadk.dts   |  37 ++++++
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 108 ++++++++++++++++++
>  2 files changed, 145 insertions(+)

DTS cannot be a dependency for driver changes. Organize your patchset
correctly or fix the dependency.

Best regards,
Krzysztof
RE: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes
Posted by Pritam Manohar Sutar 3 months, 3 weeks ago 
Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 16 June 2025 01:43 PM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> Cc: vkoul@kernel.org; kishon@kernel.org; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; alim.akhtar@samsung.com;
> andre.draszik@linaro.org; peter.griffin@linaro.org; kauschluss@disroot.org;
> ivo.ivanov.ivanov1@gmail.com; m.szyprowski@samsung.com;
> s.nawrocki@samsung.com; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
> rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB
> and USB-phy nodes
> 
> On Fri, Jun 13, 2025 at 11:26:07AM GMT, Pritam Manohar Sutar wrote:
> > Add USB controller and USB PHY controller nodes for this SoC.
> >
> > The USB controller has following features:
> > * Dual Role Device (DRD) controller
> > * DWC3 compatible
> > * Supports USB 3.0 host and USB 3.0 device interfaces but phy
> >   controller capability is limited to USB 2.0.
> > * Supports  full-speed (12 Mbps) and high-speed (480 Mbps) modes with
> >   USB device 2.0 interface
> > * Supports on-chip USB PHY transceiver
> > * Supports up to 16 bi-directional endpoints (that includes control
> >   endpoint 0)
> > * Complies with xHCI 1.1 specification
> >
> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> > ---
> >  .../boot/dts/exynos/exynosautov920-sadk.dts   |  37 ++++++
> >  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 108
> > ++++++++++++++++++
> >  2 files changed, 145 insertions(+)
> 
> DTS cannot be a dependency for driver changes. Organize your patchset
> correctly or fix the dependency.
> 

ExynosAutov920 has three types of the phy controllers (please check block diagram mentioned in cover-letter https://lore.kernel.org/linux-phy/20250613055613.866909-1-pritam.sutar@samsung.com/)
1. HS phy (synopsys phy version v303), similar as existing exynos850.
2. SS phy in combo that that suppors only SS+, SS
3. HS phy (synopsys phy version v400) in 'Add-on' HS phy in combo phy (with 2nd phy). Different from 1st phy in case of  reg offsets and bits.

This implementation follows below sequence to post patches for above phys
1. schema 
2. driver changes
3. DTS changes 

Please elaborate your comment. Do you want these DTS related patches in separate patch-set series (not with this patch-set)?

> Best regards,
> Krzysztof


Thank you.

Regards,
Pritam

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