Add device tree binding documentation for the ASPEED PCIe Root Complex
controller. This binding describes the required and optional properties
for configuring the PCIe RC node, including support for syscon phandles,
MSI, clocks, resets, and interrupt mapping. The schema enforces strict
property validation and provides a comprehensive example for reference.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
.../devicetree/bindings/pci/aspeed-pcie.yaml | 159 ++++++++++++++++++
1 file changed, 159 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
new file mode 100644
index 000000000000..5b50a9e2d472
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe Root Complex Controller
+
+maintainers:
+ - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description: |
+ Device tree binding for the ASPEED PCIe Root Complex controller.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-pcie
+ - aspeed,ast2700-pcie
+
+ device_type:
+ const: pci
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ description: IntX and MSI interrupt
+
+ resets:
+ items:
+ - description: Module reset
+ - description: PCIe PERST
+
+ reset-names:
+ items:
+ - const: h2x
+ - const: perst
+
+ msi-parent: true
+
+ msi_address:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: MSI address
+
+ aspeed,ahbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to ASPEED AHBC syscon.
+
+ aspeed,pciecfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to ASPEED PCIe configuration syscon.
+
+ aspeed,pciephy:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to ASPEED PCIe PHY syscon.
+
+ clocks:
+ description: PCIe BUS clock
+
+ interrupt-controller:
+ description: Interrupt controller node for handling legacy PCI interrupts.
+ type: object
+ properties:
+ '#address-cells':
+ const: 0
+ '#interrupt-cells':
+ const: 1
+ interrupt-controller: true
+
+ required:
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupt-controller
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2600-pcie
+ then:
+ required:
+ - aspeed,ahbc
+
+required:
+ - interrupts
+ - bus-range
+ - ranges
+ - resets
+ - reset-names
+ - msi-parent
+ - msi-controller
+ - aspeed,pciephy
+ - aspeed,pciecfg
+ - interrupt-map-mask
+ - interrupt-map
+ - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pcie0: pcie@1e7700C0 {
+ compatible = "aspeed,ast2600-pcie";
+ device_type = "pci";
+ reg = <0x1e7700C0 0x40>;
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x80 0xff>;
+
+ ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+ 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
+
+ resets = <&syscon ASPEED_RESET_H2X>,
+ <&syscon ASPEED_RESET_PCIE_RC_O>;
+ reset-names = "h2x", "perst";
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcierc1_default>;
+
+ #interrupt-cells = <1>;
+ msi-parent = <&pcie0>;
+ msi-controller;
+ msi_address = <0x1e77005C>;
+
+ aspeed,ahbc = <&ahbc>;
+ aspeed,pciecfg = <&pciecfg>;
+ aspeed,pciephy = <&pcie_phy1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
--
2.43.0
On Fri, Jun 13, 2025 at 11:29:57AM +0800, Jacky Chou wrote: > Add device tree binding documentation for the ASPEED PCIe Root Complex > controller. This binding describes the required and optional properties > for configuring the PCIe RC node, including support for syscon phandles, > MSI, clocks, resets, and interrupt mapping. The schema enforces strict > property validation and provides a comprehensive example for reference. > > Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> > --- > .../devicetree/bindings/pci/aspeed-pcie.yaml | 159 ++++++++++++++++++ > 1 file changed, 159 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > new file mode 100644 > index 000000000000..5b50a9e2d472 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > @@ -0,0 +1,159 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ASPEED PCIe Root Complex Controller > + > +maintainers: > + - Jacky Chou <jacky_chou@aspeedtech.com> > + > +description: | > + Device tree binding for the ASPEED PCIe Root Complex controller. > + > +properties: > + compatible: > + enum: > + - aspeed,ast2600-pcie > + - aspeed,ast2700-pcie > + > + device_type: > + const: pci > + > + reg: > + maxItems: 1 > + > + ranges: > + minItems: 2 > + maxItems: 2 > + > + interrupts: > + description: IntX and MSI interrupt > + > + resets: > + items: > + - description: Module reset > + - description: PCIe PERST > + > + reset-names: > + items: > + - const: h2x > + - const: perst > + > + msi-parent: true > + > + msi_address: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: MSI address What's this for? > + > + aspeed,ahbc: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED AHBC syscon. > + > + aspeed,pciecfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED PCIe configuration syscon. > + > + aspeed,pciephy: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED PCIe PHY syscon. Use the phy binding and make the phy control a separate driver. Rob
On 13/06/2025 05:29, Jacky Chou wrote: > Add device tree binding documentation for the ASPEED PCIe Root Complex > controller. This binding describes the required and optional properties > for configuring the PCIe RC node, including support for syscon phandles, > MSI, clocks, resets, and interrupt mapping. The schema enforces strict > property validation and provides a comprehensive example for reference. > > Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> > --- > .../devicetree/bindings/pci/aspeed-pcie.yaml | 159 ++++++++++++++++++ > 1 file changed, 159 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml > new file mode 100644 > index 000000000000..5b50a9e2d472 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml Same comments. > @@ -0,0 +1,159 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ASPEED PCIe Root Complex Controller > + > +maintainers: > + - Jacky Chou <jacky_chou@aspeedtech.com> > + > +description: | Do not need '|' unless you need to preserve formatting. > + Device tree binding for the ASPEED PCIe Root Complex controller. No, describe the hardware. Your current description is 100% redundant. It is never useful to say in DT binding description that it is a DT binding. It cannot be anything else, can it? > + > +properties: > + compatible: > + enum: > + - aspeed,ast2600-pcie > + - aspeed,ast2700-pcie > + > + device_type: > + const: pci You need to include proper pci schema and drop all redundant properties. Look at other schemas. > + > + reg: > + maxItems: 1 > + > + ranges: > + minItems: 2 > + maxItems: 2 > + > + interrupts: > + description: IntX and MSI interrupt Need to list the items. Look at other schemas. > + > + resets: > + items: > + - description: Module reset > + - description: PCIe PERST > + > + reset-names: > + items: > + - const: h2x > + - const: perst > + > + msi-parent: true > + > + msi_address: Where is this property defined? I do not see in kernel nor in dtschema. Drop and use existing properties. I am not even talking about coding style... > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: MSI address > + > + aspeed,ahbc: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED AHBC syscon. For what purpose? > + > + aspeed,pciecfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED PCIe configuration syscon. For what purpose? > + > + aspeed,pciephy: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to ASPEED PCIe PHY syscon. For what purpose? > + > + clocks: > + description: PCIe BUS clock Missing constraints. Just open any other binding and do not implement things diferently. > + > + interrupt-controller: > + description: Interrupt controller node for handling legacy PCI interrupts. > + type: object > + properties: > + '#address-cells': > + const: 0 > + '#interrupt-cells': > + const: 1 > + interrupt-controller: true > + > + required: > + - '#address-cells' > + - '#interrupt-cells' > + - interrupt-controller > + > + additionalProperties: false > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + - if: > + properties: > + compatible: > + contains: > + const: aspeed,ast2600-pcie > + then: > + required: > + - aspeed,ahbc else: make it false > + > +required: > + - interrupts > + - bus-range > + - ranges > + - resets > + - reset-names > + - msi-parent > + - msi-controller > + - aspeed,pciephy > + - aspeed,pciecfg > + - interrupt-map-mask > + - interrupt-map > + - interrupt-controller Messed order, missing properties. Open other bindings... > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/ast2600-clock.h> > + > + apb { > + #address-cells = <1>; > + #size-cells = <1>; > + > + pcie0: pcie@1e7700C0 { > + compatible = "aspeed,ast2600-pcie"; > + device_type = "pci"; > + reg = <0x1e7700C0 0x40>; Lower case hex. Please follow carefully DTS coding style. Best regards, Krzysztof
© 2016 - 2025 Red Hat, Inc.