Add compatible string for Exynos7870 DSIM bridge controller. The
devicetree node requires four clock sources, named:
- bus_clk
- phyclk_mipidphy0_bitclkdiv8
- phyclk_mipidphy0_rxclkesc0
- sclk_mipi
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
---
.../bindings/display/bridge/samsung,mipi-dsim.yaml | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index 1acad99f396527192b6853f0096cfb8ae5669e6b..887f3ba1edd24a177a766b1b523d0c197ff1123a 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -24,6 +24,7 @@ properties:
- samsung,exynos5410-mipi-dsi
- samsung,exynos5422-mipi-dsi
- samsung,exynos5433-mipi-dsi
+ - samsung,exynos7870-mipi-dsi
- fsl,imx8mm-mipi-dsim
- fsl,imx8mp-mipi-dsim
- items:
@@ -144,6 +145,31 @@ required:
allOf:
- $ref: ../dsi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7870-mipi-dsi
+
+ then:
+ properties:
+ clocks:
+ minItems: 4
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: phyclk_mipidphy0_bitclkdiv8
+ - const: phyclk_mipidphy0_rxclkesc0
+ - const: sclk_mipi
+
+ ports:
+ required:
+ - port@0
+
+ required:
+ - ports
+
- if:
properties:
compatible:
--
2.49.0
On 12/06/2025 17:18, Kaustabh Chakraborty wrote: > Add compatible string for Exynos7870 DSIM bridge controller. The > devicetree node requires four clock sources, named: > - bus_clk > - phyclk_mipidphy0_bitclkdiv8 > - phyclk_mipidphy0_rxclkesc0 > - sclk_mipi > > Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> > --- > .../bindings/display/bridge/samsung,mipi-dsim.yaml | 26 ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml > index 1acad99f396527192b6853f0096cfb8ae5669e6b..887f3ba1edd24a177a766b1b523d0c197ff1123a 100644 > --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml > +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml > @@ -24,6 +24,7 @@ properties: > - samsung,exynos5410-mipi-dsi > - samsung,exynos5422-mipi-dsi > - samsung,exynos5433-mipi-dsi > + - samsung,exynos7870-mipi-dsi > - fsl,imx8mm-mipi-dsim > - fsl,imx8mp-mipi-dsim > - items: > @@ -144,6 +145,31 @@ required: > > allOf: > - $ref: ../dsi-controller.yaml# > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos7870-mipi-dsi > + > + then: > + properties: > + clocks: > + minItems: 4 maxItems: 4 > + > + clock-names: > + items: > + - const: bus_clk > + - const: phyclk_mipidphy0_bitclkdiv8 > + - const: phyclk_mipidphy0_rxclkesc0 > + - const: sclk_mipi Does any existing driver code actually depends on the names? If not, we switched in Samsung in general to names matching the input or the function, not the name of provider. bus, bit (or bitdiv?), rx or esc0, sclk Best regards, Krzysztof
On 2025-06-18 10:00, Krzysztof Kozlowski wrote: > On 12/06/2025 17:18, Kaustabh Chakraborty wrote: >> Add compatible string for Exynos7870 DSIM bridge controller. The >> devicetree node requires four clock sources, named: >> - bus_clk >> - phyclk_mipidphy0_bitclkdiv8 >> - phyclk_mipidphy0_rxclkesc0 >> - sclk_mipi >> >> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> >> --- >> .../bindings/display/bridge/samsung,mipi-dsim.yaml | 26 ++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >> index 1acad99f396527192b6853f0096cfb8ae5669e6b..887f3ba1edd24a177a766b1b523d0c197ff1123a 100644 >> --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >> @@ -24,6 +24,7 @@ properties: >> - samsung,exynos5410-mipi-dsi >> - samsung,exynos5422-mipi-dsi >> - samsung,exynos5433-mipi-dsi >> + - samsung,exynos7870-mipi-dsi >> - fsl,imx8mm-mipi-dsim >> - fsl,imx8mp-mipi-dsim >> - items: >> @@ -144,6 +145,31 @@ required: >> >> allOf: >> - $ref: ../dsi-controller.yaml# >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: samsung,exynos7870-mipi-dsi >> + >> + then: >> + properties: >> + clocks: >> + minItems: 4 > > maxItems: 4 Will replace. maxItems == minItems implicit if maxItems present and minItems absent. > >> + >> + clock-names: >> + items: >> + - const: bus_clk >> + - const: phyclk_mipidphy0_bitclkdiv8 >> + - const: phyclk_mipidphy0_rxclkesc0 >> + - const: sclk_mipi > > Does any existing driver code actually depends on the names? If not, we > switched in Samsung in general to names matching the input or the > function, not the name of provider. bus, bit (or bitdiv?), rx or esc0, sclk Yeah, Exynos5433 uses it. Code is here [1]. Though, I could get around this if you would like to. Would need to add a few more patches. PS: bitdiv8 should actually be byte. bit clock frequency used in data transmission divided by 8 covers a byte. [1] https://elixir.bootlin.com/linux/v6.16-rc2/source/drivers/gpu/drm/bridge/samsung-dsim.c#L227 > > > Best regards, > Krzysztof
On 18/06/2025 16:27, Kaustabh Chakraborty wrote: > On 2025-06-18 10:00, Krzysztof Kozlowski wrote: >> On 12/06/2025 17:18, Kaustabh Chakraborty wrote: >>> Add compatible string for Exynos7870 DSIM bridge controller. The >>> devicetree node requires four clock sources, named: >>> - bus_clk >>> - phyclk_mipidphy0_bitclkdiv8 >>> - phyclk_mipidphy0_rxclkesc0 >>> - sclk_mipi >>> >>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> >>> --- >>> .../bindings/display/bridge/samsung,mipi-dsim.yaml | 26 ++++++++++++++++++++++ >>> 1 file changed, 26 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >>> index 1acad99f396527192b6853f0096cfb8ae5669e6b..887f3ba1edd24a177a766b1b523d0c197ff1123a 100644 >>> --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >>> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml >>> @@ -24,6 +24,7 @@ properties: >>> - samsung,exynos5410-mipi-dsi >>> - samsung,exynos5422-mipi-dsi >>> - samsung,exynos5433-mipi-dsi >>> + - samsung,exynos7870-mipi-dsi >>> - fsl,imx8mm-mipi-dsim >>> - fsl,imx8mp-mipi-dsim >>> - items: >>> @@ -144,6 +145,31 @@ required: >>> >>> allOf: >>> - $ref: ../dsi-controller.yaml# >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: samsung,exynos7870-mipi-dsi >>> + >>> + then: >>> + properties: >>> + clocks: >>> + minItems: 4 >> >> maxItems: 4 > > Will replace. maxItems == minItems implicit if maxItems present and > minItems absent. No, you need both. Add maxItemsd. Look at all or most of Exynos bindings. > >> >>> + >>> + clock-names: >>> + items: >>> + - const: bus_clk >>> + - const: phyclk_mipidphy0_bitclkdiv8 >>> + - const: phyclk_mipidphy0_rxclkesc0 >>> + - const: sclk_mipi >> >> Does any existing driver code actually depends on the names? If not, we >> switched in Samsung in general to names matching the input or the >> function, not the name of provider. bus, bit (or bitdiv?), rx or esc0, sclk > > Yeah, Exynos5433 uses it. Code is here [1]. It is fine then. > > Though, I could get around this if you would like to. Would need to add > a few more patches. If you want to work on this, then it would be useful - add clock names per variant/device and just clk_get_bulk() on supplied array. Up to you. Best regards, Krzysztof
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